IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 45/272

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5.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-
power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after
the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode,
ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3). Track-
ing can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that settling time
requirements are met (see
Section “5.2.3. Settling Time Requirements” on page
Figure 5.3. 12-Bit ADC Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
CNVSTR
(AD0STM[1:0]=10
)
SAR Clocks
Low Power
ADC0TM=1
or Convert
ADC0TM=0
Track Or Convert
B. ADC Timing for Internal Trigger Sources
Timer 2, Timer 3 Overflow;
Write '1' to AD0BUSY
(AD0STM[1:0]=00, 01, 11)
1
SAR Clocks
Low Power
ADC0TM=1
or Convert
1
SAR Clocks
Track or
ADC0TM=0
Convert
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Track
Convert
Convert
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Convert
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Convert
Rev. 1.4
C8051F020/1
46).
Low Power Mode
Track
Low Power Mode
Track
45