IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
19.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
19.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master, and an
input when SPI0 is operating as a slave. Data is transferred most-significant bit first.
19.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master, and an
output when SPI0 is operating as a slave. Data is transferred most-significant bit first. A SPI slave places the MISO
pin in a high-impedance state when the slave is not selected.
19.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchro-
nize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when
operating as a master.
19.1.4. Slave Select (NSS)
The slave select (NSS) signal is an input used to select SPI0 as a slave, or to disable SPI0 as a master. Note that the
NSS signal is always an input to SPI0; with SPI0 operating as a master, slave select signals must be output via general
purpose port I/O pins. See Figure 19.2 for a typical configuration; see Section
ority Crossbar
Decoder” on page
163
The NSS signal must be low to initiate a transfer with SPI0 as a slave; SPI0 will exit slave mode when NSS is
released high. Note that received data is not latched into the receive buffer until NSS is high. For multiple-byte trans-
fers, NSS must be released high for at least 4 system clocks following each byte that is received by the SPI0 slave.
Figure 19.2. Typical SPI Interconnection
GPIO
Master
Device
MISO
MOSI
SCK
198
for general purpose port configuration.
NSS
NSS
Slave
Slave
Device
Device
Device
Rev. 1.4
“17.1. Ports 0 through 3 and the Pri-
NSS
Slave
VDD
MISO
MOSI
SCK