IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
Figure 17.21. P4: Port4 Data Register
R/W
R/W
R/W
P4.7
P4.6
P4.5
Bit7
Bit6
Bit5
Bits7-0:
P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
See
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on
page 145
for more information.
Figure 17.22. P5: Port5 Data Register
R/W
R/W
R/W
P5.7
P5.6
P5.5
Bit7
Bit6
Bit5
Bits7-0:
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note:
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM”
on page 145
for more information about the External Memory Interface.
180
R/W
R/W
R/W
R/W
P4.4
P4.3
P4.2
P4.1
Bit4
Bit3
Bit2
Bit1
R/W
R/W
R/W
R/W
P5.4
P5.3
P5.2
P5.1
Bit4
Bit3
Bit2
Bit1
Rev. 1.4
R/W
Reset Value
P4.0
11111111
Bit0
SFR Address:
0x84
R/W
Reset Value
P5.0
11111111
Bit0
SFR Address:
0x85