IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 165/272

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17.1.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the
associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting P3MDOUT.7 to a
logic 0 and P3.7 to a logic 1.
If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example
RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled.
17.1.4. External Interrupts (IE6 and IE7)
In addition to the external interrupts /INT0 and /INT1, whose Port pins are allocated and assigned by the Crossbar,
P3.6 and P3.7 can be configured to generate edge sensitive interrupts; these interrupts are configurable as falling- or
rising-edge sensitive using the IE6CF (P3IF.2) and IE7CF (P3IF.3) bits. When an active edge is detected on P3.6 or
P3.7, a corresponding External Interrupt flag (IE6 or IE7) will be set to a logic 1 in the P3IF register (See
Figure 17.19). If the associated interrupt is enabled, an interrupt will be generated and the CPU will vector to the
associated interrupt vector location. See
interrupts.
17.1.5. Weak Pull-ups
By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about
100 k) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the
Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is
driving a logic 0; that is, an output pin will not contend with its own pull-up device. The weak pull-up device can also
be explicitly disabled on a Port 1 pin by configuring the pin as an Analog Input, as described below.
17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])
The pins on Port 1 can serve as analog inputs to the ADC1 analog MUX. A Port pin is configured as an Analog Input
by writing a logic 0 to the associated bit in the P1MDIN register (see Figure 17.13). All Port pins default to a Digital
Input mode. Configuring a Port pin as an analog input:
1.
Disables the digital input path from the pin. This prevents additional power supply current
from being drawn when the voltage at the pin is near VDD / 2. A read of the Port Data bit will
return a logic 0 regardless of the voltage at the Port pin.
2.
Disables the weak pull-up device on the pin.
3.
Causes the Crossbar to “skip over” the pin when allocating Port pins for digital peripherals.
Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled. Therefore, the
associated P1MDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0 (Open-Drain output
mode), and the associated Port Data bits should be set to logic 1 (high-impedance). Also note that it is not required to
configure a Port pin as an Analog Input in order to use it as an input to the ADC1 MUX; however, it is strongly rec-
ommended. See
Section “7. ADC1 (8-Bit ADC)” on page 75
Section “12.3. Interrupt Handler” on page 116
for more information about ADC1.
Rev. 1.4
C8051F020/1/2/3
for more information about
165