IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 183/272

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18.
SYSTEM MANAGEMENT BUS / I
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I
system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the
data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail-
able to accommodate devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides
control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP
control and generation. SMBus0 is controlled by SFRs as described in
Figure 18.1. SMBus0 Block Diagram
SFR Bus
SMB0CN
SMB0STA
B
E
S
S
S
A
F
T
S
S
S
S
U
N
T
T
I
A
T
O
T
T
T
T
S
S
A
O
E
E
A
A
A
A
Y
M
7
6
5
4
B
SMBUS CONTROL LOGIC
Arbitration
SMBUS
Interrupt
SCL Synchronization
Request
IRQ
Status Generation
SCL Generation (Master Mode)
IRQ Generation
B
A
B
A
0000000b
7 MSBs
7
8
S
S
S
S
S
S
S
L
L
L
L
L
L
L
V
V
V
V
V
V
V
G
6
5
4
3
2
1
0
C
SMB0ADR
SFR Bus
2
C BUS (SMBUS0)
2
C serial bus. Reads and writes to the interface by the
Section 18.4 on page
SMB0CR
S
S
S
S
C
C
C
C
C
C
C
C
T
T
T
T
R
R
R
R
R
R
R
R
A
A
A
A
7
6
5
4
3
2
1
0
3
2
1
0
Clock Divide
SYSCLK
Logic
FILTER
SCL
Control
SDA
Data Path
Control
Control
8
SMB0DAT
7
6
5
4
3
2
1
0
FILTER
8
1
0
Read
Write to
SMB0DAT
SMB0DAT
Rev. 1.4
C8051F020/1/2/3
189.
SCL
N
C
R
O
S
Port I/O
S
B
A
R
SDA
N
183