C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 151

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
16.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space.
16.5.4. External Only
When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visi-
ble to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 4k boundary.
16.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to devices having
different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths,
and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through
EMI0TC, shown in Figure 16.6, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters
defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip
XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed opera-
tions, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the mini-
mum execution time of an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 SYSCLKs for
/ALE, 1 for /RD or /WR + 4 SYSCLKs). The programmable setup and hold times default to the maximum delay set-
tings after a reset.
Table 16.1 lists the AC parameters for the External Memory Interface, and Figure 16.7 through Figure 16.11 show the
timing diagrams for the different External Memory Interface modes and MOVX operations
Effective addresses below the 4k boundary will access on-chip XRAM space.
Effective addresses beyond the 4k boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the
Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank
Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identi-
cal behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to
manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective
address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits
of the Address Bus A[15:0] are driven during the off-chip transaction.
Rev. 1.4
C8051F020/1/2/3
151

Related parts for C8051F021-GQ