IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Page 151
152
Page 152
153
Page 153
154
Page 154
155
Page 155
156
Page 156
157
Page 157
158
Page 158
159
Page 159
160
Page 160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
Page 151/272

Download datasheet (2Mb)Embed
PrevNext
16.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space.
Effective addresses below the 4k boundary will access on-chip XRAM space.
Effective addresses beyond the 4k boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the
Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank
Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
16.5.4. External Only
When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visi-
ble to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 4k boundary.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identi-
cal behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to
manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective
address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits
of the Address Bus A[15:0] are driven during the off-chip transaction.
16.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to devices having
different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths,
and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through
EMI0TC, shown in Figure 16.6, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters
defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip
XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed opera-
tions, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the mini-
mum execution time of an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 SYSCLKs for
/ALE, 1 for /RD or /WR + 4 SYSCLKs). The programmable setup and hold times default to the maximum delay set-
tings after a reset.
Table 16.1 lists the AC parameters for the External Memory Interface, and Figure 16.7 through Figure 16.11 show the
timing diagrams for the different External Memory Interface modes and MOVX operations
C8051F020/1/2/3
Rev. 1.4
151