IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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6.
ADC0 (10-BIT ADC, C8051F022/3 ONLY)
The ADC0 subsystem for the C8051F022/3 consists of a 9-channel, configurable analog multiplexer (AMUX0), a
programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and Programmable Window Detector (see block diagram in Figure 6.1). The AMUX0, PGA0, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in
REFERENCE (C8051F020/2)” on page 91
(C8051F021/3)” on page 93
for C8051F021/3 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is
in low power shutdown when this bit is logic 0.
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
ADC0GTH
ADC0GTL
AIN0
+
AIN1
-
AIN2
+
AIN3
-
9-to-1
AMUX
AIN4
+
(SE or
DIFF)
AIN5
-
AIN6
+
AIN7
-
TEMP
SENSOR
AGND
AMX0CF
AMX0SL
6.1.
Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected
to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX input pairs can be
programmed to operate in either differential or single-ended mode. This allows the user to select the best measure-
ment technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to
all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register
AMX0SL (Figure 6.6), and the Configuration register AMX0CF (Figure 6.7). The table in Figure 6.6 shows AMUX
functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount
determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 6.7). The
PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
for C8051F020/2 devices, or
Section “10. VOLTAGE REFERENCE
ADC0LTH
ADC0LTL
AV+
AD0EN
AV+
10-Bit
+
SAR
X
-
ADC
AGND
ADC0CF
ADC0CN
Rev. 1.4
C8051F022/3
Section “9. VOLTAGE
20
Comb.
AD0WINT
Logic
10
10
00
AD0BUSY (W)
01
Timer 3 Overflow
Start Conversion
10
CNVSTR
11
Timer 2 Overflow
59