IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
Page 91/272

Download datasheet (2Mb)Embed
PrevNext
9.
VOLTAGE REFERENCE (C8051F020/2)
The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference
input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage refer-
ence output. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power sup-
ply voltage, via the VREF multiplexers shown in Figure 9.1.
The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator
and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system
components or to the voltage reference input pins shown in Figure 9.1. Bypass capacitors of 0.1 µF and 4.7 µF are
recommended from the VREF pin to AGND, as shown in Figure 9.1. See Table 9.1 for voltage reference specifica-
tions.
The Reference Control Register, REF0CN (defined in Figure 9.2) enables/disables the internal reference generator
and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the on-board reference
generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,
the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the
buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,
BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0.
Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage refer-
ence is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are
being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0
and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference circuit are
given in Table 9.1.
Figure 9.1. Voltage Reference Functional Block Diagram
VDD
External
R1
Voltage
Reference
Circuit
DGND
4.7F
0.1F
Recommended Bypass
Capacitors
C8051F020/1/2/3
REF0CN
AV+
1
VREF1
0
VREF0
0
1
DAC0
VREFD
Ref
DAC1
VREF
x2
REFBE
Rev. 1.4
ADC1
Ref
ADC0
Ref
BIASE
Bias to
EN
ADCs,
DACs
1.2V
Band-Gap
91