IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
13.1. Power-on Reset
The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD
rises above the V
level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for the Elec-
RST
trical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms
VDD Monitor timeout in order to allow the VDD supply to stabilize.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags
in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause program exe-
cution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the
cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset.
The VDD monitor function is enabled by tying the MONEN pin directly to VDD. This is the recommended
configuration for the MONEN pin.
.
2.70
V
RST
2.55
2.0
1.0
/RST
Logic HIGH
Logic LOW
13.2. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below V
drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level above VRST, the CIP-51
will leave the reset state in the same manner as that for the power-on reset (see Figure 13.2). Note that even though
internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped
below the level required for data retention. If the PORSF flag is set to logic 1, the data may no longer be valid.
128
Figure 13.2. Reset Timing
100ms
Power-On Reset
VDD Monitor Reset
Rev. 1.4
t
100ms
, the power supply monitor will
RST