IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 168/272

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C8051F020/1/2/3
17.1.8. Crossbar Pin Assignment Example
In this example (Figure 17.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1,
/INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in Multiplexed
mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the
voltages at these pins can be measured by ADC1. The configuration steps are as follows:
1.
XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, INT0E = 1, INT1E
= 1, and EMIFLE = 1. Thus: XBR0 = 0x05, XBR1 = 0x14, and XBR2 = 0x02.
2.
We configure the External Memory Interface to use Multiplexed mode and to appear on the
Low ports. PRTSEL = 0, EMD2 = 0.
3.
We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (P1.4,
P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0).
4.
We enable the Crossbar by setting XBARE = 1: XBR2 = 0x46.
-
UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0.
-
The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to SCL.
-
UART1 is next in priority order, so P0.4 is assigned to TX1. Because the External Memory Inter-
face is selected on the lower Ports, EMIFLE = 1, which causes the Crossbar to skip P0.6 (/RD) and
P0.7 (/WR). Because the External Memory Interface is configured in Multiplexed mode, the Cross-
bar will also skip P0.5 (ALE). RX1 is assigned to the next non-skipped pin, which in this case is
P1.0.
-
/INT0 is next in priority order, so it is assigned to P1.1.
-
P1MDIN is set to 0xE3, which configures P1.2, P1.3, and P1.4 as Analog Inputs, causing the
Crossbar to skip these pins.
-
/INT1 is next in priority order, so it is assigned to the next non-skipped pin, which is P1.5.
-
The External Memory Interface will drive Ports 2 and 3 (denoted by red dots in Figure 17.6) during
the execution of an off-chip MOVX instruction.
5.
We set the UART0 TX pin (TX0, P0.0), UART1 TX pin (TX1, P0.4), ALE, /RD, /WR
(P0.[7:3]) outputs to Push-Pull by setting P0MDOUT = 0xF1.
6.
We configure the output modes of the EMIF Ports (P2, P3) to Push-Pull by setting P2MDOUT
= 0xFF and P3MDOUT = 0xFF.
7.
We explicitly disable the output drivers on the 3 Analog Input pins by setting P1MDOUT =
0x00 (configure outputs to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance
state).
168
Rev. 1.4