IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 201/272

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19.4. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg-
ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special
function registers related to the operation of the SPI0 Bus are described in the following section.
Figure 19.5. SPI0CFG: SPI0 Configuration Register
R/W
R/W
R
CKPHA
CKPOL
BC2
Bit7
Bit6
Bit5
Bit7:
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
Bit6:
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Bits5-3:
BC2-BC0: SPI0 Bit Count.
Indicates which of the up to 8 bits of the SPI0 word have been transmitted.
BC2-BC0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bits2-0:
SPIFRS2-SPIFRS0: SPI0 Frame Size.
These three bits determine the number of bits to shift in/out of the SPI0 shift register during a data
transfer in master mode. They are ignored in slave mode.
SPIFRS
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
C8051F020/1/2/3
R
R
R/W
BC1
BC0
SPIFRS2
SPIFRS1
Bit4
Bit3
Bit2
BIT Transmitted
0
Bit 0 (LSB)
1
Bit 1
0
Bit 2
1
Bit 3
0
Bit 4
1
Bit 5
0
Bit 6
1
Bit 7 (MSB)
Bits Shifted
0
1
1
2
0
3
1
4
0
5
1
6
0
7
1
8
Rev. 1.4
R/W
R/W
Reset Value
SPIFRS0
00000111
Bit1
Bit0
SFR Address:
0x9A
201