IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Figure 17.19. P3IF: Port3 Interrupt Flag Register
R/W
R/W
R
IE7
IE6
-
Bit7
Bit6
Bit5
Bit7:
IE7: External Interrupt 7 Pending Flag
0: No falling edge has been detected on P3.7 since this bit was last cleared.
1: This flag is set by hardware when a falling edge on P3.7 is detected.
Bit6:
IE6: External Interrupt 6 Pending Flag
0: No falling edge has been detected on P3.6 since this bit was last cleared.
1: This flag is set by hardware when a falling edge on P3.6 is detected.
Bits5-4:
UNUSED. Read = 00b, Write = don’t care.
Bit3:
IE7CF: External Interrupt 7 Edge Configuration
0: External Interrupt 7 triggered by a falling edge on the IE7 input.
1: External Interrupt 7 triggered by a rising edge on the IE7 input.
Bit2:
IE6CF: External Interrupt 6 Edge Configuration
0: External Interrupt 6 triggered by a falling edge on the IE6 input.
1: External Interrupt 6 triggered by a rising edge on the IE6 input.
Bits1-0:
UNUSED. Read = 00b, Write = don’t care.
17.2. Ports 4 through 7 (C8051F020/2 only)
All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the
associated Port Data registers (See Figure 17.21, Figure 17.22, Figure 17.23, and Figure 17.24), a set of SFRs which
are byte-addressable.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of
whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution
of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV
operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data register, not
the state of the Port pins themselves, which is read.
17.2.1. Configuring Ports which are not Pinned Out
Although P4, P5, P6, and P7 are not brought out to pins on the C8051F021/3 devices, the Port Data registers are still
present and can be used by software. Because the digital input paths also remain active, it is recommended that these
pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipation arising from the inputs floating to
non-valid logic levels. This condition can be prevented by any of the following:
1.
Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.
2.
Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing P74OUT = 0xFF.
3.
Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data regis-
ters: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.
17.2.2. Configuring the Output Modes of the Port Pins
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configura-
tion, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1
will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the
C8051F020/1/2/3
R
R/W
R/W
R/W
-
IE7CF
IE6CF
Bit4
Bit3
Bit2
Bit1
Rev. 1.4
R/W
Reset Value
-
-
00000000
Bit0
SFR Address:
0xAD
177