C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 127

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
13.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits the reset state.
This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low
until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at 2 MHz. Refer to Section
the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Section
“13.8. Watchdog Timer
location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source
is described in the following sections.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known state
Interrupts and timers are disabled.
RESET SOURCES
(Port
XTAL1
XTAL2
I/O)
CP0+
CP0-
Generator
Reset” on page 129). Once the system clock source is stable, program execution begins at
Internal
Clock
Crossbar
OSC
Comparator0
CNVSTR
(CNVSTR
+
-
“14.
enable)
reset
enable)
OSCILLATORS” on page
(CP0
reset
Clock Select
System
Clock
Figure 13.1. Reset Sources
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
VDD
Core
Handler
Rev. 1.4
EN
WDT
PRE
Supply
Monitor
+
-
Software Reset
System Reset
135
Timeout
Supply
Reset
for information on selecting and configuring
C8051F020/1/2/3
(wired-OR)
Reset
Funnel
/RST
127

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