IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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Page 127/272

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13.
RESET SOURCES
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits the reset state.
This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low
until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at 2 MHz. Refer to Section
“14.
the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Section
“13.8. Watchdog Timer
Reset” on page 129). Once the system clock source is stable, program execution begins at
location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source
is described in the following sections.
CNVSTR
(Port
Crossbar
I/O)
(CNVSTR
reset
enable)
Comparator0
CP0+
+
-
CP0-
Internal
Clock
Generator
XTAL1
OSC
XTAL2
OSCILLATORS” on page
135
for information on selecting and configuring
Figure 13.1. Reset Sources
VDD
Supply
Monitor
Supply
+
Reset
-
Timeout
(CP0
reset
enable)
Missing
WDT
Clock
Detector
(one-
shot)
EN
EN
PRE
System
Software Reset
Clock
CIP-51
Microcontroller
Clock Select
System Reset
Core
Extended Interrupt
Handler
Rev. 1.4
C8051F020/1/2/3
/RST
(wired-OR)
Reset
Funnel
127