IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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4.
PINOUT AND PACKAGE DEFINITIONS
Pin Numbers
Name
F020
F021
F022
F023
VDD
37, 64,
24, 41,
90
57
DGND
38, 63,
25, 40,
89
56
AV+
11, 14
6
AGND
10, 13
5
TMS
1
58
TCK
2
59
TDI
3
60
TDO
4
61
/RST
5
62
XTAL1
26
17
XTAL2
27
18
MONEN
28
19
VREF
12
7
VREFA
8
VREF0
16
VREF1
17
VREFD
15
Table 4.1. Pin Definitions
Type
Description
Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
Analog Ground. Must be tied to Ground.
D In
JTAG Test Mode Select with internal pull-up.
D In
JTAG Test Clock with internal pull-up.
D In
JTAG Test Data Input with internal pull-up. TDI is latched on the
rising edge of TCK.
D Out JTAG Test Data Output with internal pull-up. Data is shifted out on
TDO on the falling edge of TCK. TDO output is a tri-state driver.
D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven
low when VDD is <2.7 V and MONEN is high. An external source
can initiate a system reset by driving this pin low.
A In
Crystal Input. This pin is the return for the internal oscillator circuit
for a crystal or ceramic resonator. For a precision internal clock,
connect a crystal or ceramic resonator from XTAL1 to XTAL2. If
overdriven by an external CMOS clock, this becomes the system
clock.
A Out Crystal Output. This pin is the excitation driver for a crystal or
ceramic resonator.
D In
VDD Monitor Enable. When tied high, this pin enables the internal
VDD monitor, which forces a system reset when VDD is < 2.7 V.
When tied low, the internal VDD monitor is disabled.
A I/O Bandgap Voltage Reference Output (all devices).
DAC Voltage Reference Input (F021/3 only).
A In
ADC0 and ADC1 Voltage Reference Input.
A In
ADC0 Voltage Reference Input.
A In
ADC1 Voltage Reference Input.
A In
DAC Voltage Reference Input.
Rev. 1.4
C8051F020/1/2/3
33