IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while
allowing additional code to be programmed in remaining program memory space later.
The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address, and
the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but exclud-
ing) the SRL address. Software in the upper partition can execute code in the lower partition, but is prohibited from
reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the upper
partition with a source address in the lower partition will always return a data value of 0x00.) Software running in the
lower partition can access locations in both the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added
firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a predeter-
mined location in the upper partition. If entry points are published, software running in the upper partition may exe-
cute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters may be
passed to the program code running in the lower partition either through the typical method of placing them on the
stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the FLASH Access Register. The 16-bit SRL address is calculated
as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte bound-
aries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a 512
boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address to
0x0000 and allowing read access to all locations in program memory space by default.
Figure 15.2. FLACL: FLASH Access Limit
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bits 7-0: FLACL: FLASH Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit address. The
entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of
FLACL. A write to this register sets the FLASH Access Limit. This register can only be written once
after any reset. Any subsequent writes are ignored until the next reset.
142
R/W
R/W
R/W
R/W
Bit4
Bit3
Bit2
Bit1
Rev. 1.4
R/W
Reset Value
00000000
Bit0
SFR Address:
0xB7