IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part NumberC8051F021-GQ
DescriptionIC 8051 MCU 64K FLASH 64TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F021-GQ datasheets
 


Specifications of C8051F021-GQ

Program Memory TypeFLASHProgram Memory Size64KB (64K x 8)
Package / Case64-TQFP, 64-VQFPCore Processor8051
Core Size8-BitSpeed25MHz
ConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o32Ram Size4.25K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 VData ConvertersA/D 8x8b, 8x12b; D/A 2x12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesC8051F0xCore8051
Data Bus Width8 bitData Ram Size4.25 KB
Interface TypeI2C/SMBus/SPI/UARTMaximum Clock Frequency25 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage2.7 V to 3.6 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsPK51, CA51, A51, ULINK2
Development Tools By SupplierC8051F020DKMinimum Operating Temperature- 40 C
On-chip Adc8-ch x 8-bit or 8-ch x 12-bitOn-chip Dac2-ch x 12-bit
No. Of I/o's32Ram Memory Size4352Byte
Cpu Speed25MHzNo. Of Timers5
No. Of Pwm Channels5Rohs CompliantYes
Data Rom Size64 KBA/d Bit Size12 bit
A/d Channels Available8Height1.05 mm
Length10 mmSupply Voltage (max)3.6 V
Supply Voltage (min)2.7 VWidth10 mm
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size-Other names336-1201
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C8051F020/1/2/3
18.4. SMBus Special Function Registers
The SMBus0 serial interface is accessed and controlled through five SFRs: SMB0CN Control Register, SMB0CR
Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The
five special function registers related to the operation of the SMBus0 interface are described in the following sec-
tions.
18.4.1. Control Register
The SMBus0 Control register SMB0CN is used to configure and control the SMBus0 interface. All of the bits in the
register can be read or written by software. Two of the control bits are also affected by the SMBus0 hardware. The
Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs.
It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is cleared to logic 0 by hardware when a STOP
condition is detected on the bus.
Setting the ENSMS flag to logic 1 enables the SMBus0 interface. Clearing the ENSMB flag to logic 0 disables the
SMBus0 interface and removes it from the bus. Momentarily clearing the ENSMB flag and then resetting it to logic 1
will reset SMBus0 communication. However, ENSMB should not be used to temporarily remove a device from the
bus since the bus state information will be lost. Instead, the Assert Acknowledge (AA) flag should be used to tempo-
rarily remove the device from the bus (see description of AA flag below).
Setting the Start flag (STA, SMB0CN.5) to logic 1 will put SMBus0 in a master mode. If the bus is free, SMBus0 will
generate a START condition. If the bus is not free, SMBus0 waits for a STOP condition to free the bus and then gen-
erates a START condition after a 5 µs delay per the SMB0CR value (In accordance with the SMBus protocol, the
SMBus0 interface also considers the bus free if the bus is idle for 50 µs and no STOP condition was recognized). If
STA is set to logic 1 while SMBus0 is in master mode and one or more bytes have been transferred, a repeated
START condition will be generated. To ensure proper operation, the STO bit should be explicitly cleared to ‘0’ before
setting the STA bit to ‘1’.
When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus0 interface is in master mode, the interface
generates a STOP condition. In a slave mode, the STO flag may be used to recover from an error condition. In this
case, a STOP condition is not generated on the bus, but the SMBus hardware behaves as if a STOP condition has been
received and enters the "not addressed" slave receiver mode. Note that this simulated STOP will not cause the bus to
appear free to SMBus0. The bus will remain occupied until a STOP appears on the bus or a Bus Free Timeout occurs.
Hardware automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus.
The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hardware when the SMBus0 interface enters one of 27
possible states. If interrupts are enabled for the SMBus0 interface, an interrupt request is generated when the SI flag
is set. The SI flag must be cleared by software.
Important Note: If SI is set to logic 1 while the SCL line is low, the clock-low period of the serial clock will be
stretched and the serial transfer is suspended until SI is cleared to logic 0. A high level on SCL is not affected by the
setting of the SI flag.
The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowledge
clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACK (low level on SDA) to be sent during
the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will cause a NACK (high level
on SDA) to be sent during acknowledge cycle. After the transmission of a byte in slave mode, the slave can be tempo-
rarily removed from the bus by clearing the AA flag. The slave's own address and general call address will be
ignored. To resume operation on the bus, the AA flag must be reset to logic 1 to allow the slave's address to be recog-
nized.
Rev. 1.4
189