C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 269
Manufacturer Part Number
IC 8051 MCU 64K FLASH 64TQFP
Silicon Laboratories Inc
Specifications of C8051F021-GQ
Program Memory Type
Program Memory Size
64KB (64K x 8)
Package / Case
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
A/D 8x8b, 8x12b; D/A 2x12b
-40°C ~ 85°C
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
8-ch x 8-bit or 8-ch x 12-bit
2-ch x 12-bit
No. Of I/o's
Ram Memory Size
No. Of Timers
No. Of Pwm Channels
Data Rom Size
A/d Bit Size
A/d Channels Available
Supply Voltage (max)
Supply Voltage (min)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Figure 24.3. FLASHCON: JTAG Flash Control Register
This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT
SFLE: Scratchpad FLASH Memory Access Enable.
When this bit is set, FLASH reads and writes are directed to the 128-byte Scratchpad FLASH sector.
When SFLE is set to logic 1, FLASH accesses out of the address range 0x00-0x7F should not be
attempted. Reads/Writes out of this range will yield unpredictable results.
FLASH access directed to the 64k byte Program/Data FLASH sector.
FLASH access directed to the 128 byte Scratchpad sector.
WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASHDAT
Register per the following values:
A FLASHDAT write replaces the data in the FASHDAT register, but is otherwise ignored.
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing
the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x7DFE - 0x7DFF, the entire user space will
be erased (i.e. entire Flash memory except for Reserved area 0x7E00 - 0x7FFF).
(All other values for WRMD3-0 are reserved.)
RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASHDAT Reg-
ister per the following values:
A FLASHDAT read provides the data in the FASHDAT register, but is otherwise ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no
operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block) without
initiating an extra read.
(All other values for RDMD3-0 are reserved.)