IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part NumberMC68HC711E9CFNE2
DescriptionIC MCU 8BIT 512RAM 52-PLC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E9CFNE2 datasheet
 

Specifications of MC68HC711E9CFNE2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size12KB (12K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCProcessor SeriesHC711E
CoreHC11Data Bus Width8 bit
Data Ram Size512 BInterface TypeSCI, SPI
Maximum Clock Frequency2 MHzNumber Of Programmable I/os38
Number Of Timers8Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
On-chip Adc8 bitLead Free Status / RoHS StatusLead free / RoHS Compliant
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M68HC11E/D
REV 3.2
M68HC11E Family
Technical Data
HCMOS
Microcontroller Unit

MC68HC711E9CFNE2 Summary of contents

  • Page 1

    M68HC11E/D REV 3.2 M68HC11E Family Technical Data HCMOS Microcontroller Unit ...

  • Page 2

    blank ...

  • Page 3

    MC68HC11E Family Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

  • Page 4

    UrpuvphyÃ9h‡h To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: ...

  • Page 5

    Technical Data — M68HC11E Family Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Pin Descriptions . . . . . . ...

  • Page 6

    List of Sections AN1060 — M68HC11 Bootstrap Mode . . . . . . . . . . . . . 277 EB184 — Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR . . . ...

  • Page 7

    Technical Data — M68HC11E Family 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 M68HC11E Family — Rev. 3.2 MOTOROLA Section 1. General Description Contents . . ...

  • Page 8

    Table of Contents 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.6.5 3.3.6.6 3.3.6.7 3.3.6.8 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 Technical Data 8 Section 3. Central Processor Unit (CPU) Contents ...

  • Page 9

    M68HC11E Family — Rev. 3.2 MOTOROLA Section 4. Operating Modes and On-Chip Memory ...

  • Page 10

    Table of Contents 5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.5 5.5.1 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.7 5.7.1 5.7.2 Technical Data 10 Section 5. ...

  • Page 11

    M68HC11E Family — Rev. 3.2 MOTOROLA Section 6. Parallel Input/Output (I/O) Ports Contents . ...

  • Page 12

    Table of Contents 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.8 8.8.1 8.8.2 8.8.3 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 Technical Data 12 Section 8. Serial ...

  • Page 13

    A/D Control/Status Register . . . . . . . . . . ...

  • Page 14

    Table of Contents 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 15

    A.1 A.2 A.3 A.4 A.5 A.6 M68HC11EVBU Schematic ...

  • Page 16

    Table of Contents AN1060 — M68HC11 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . 277 EB184 — Enabling the Security Feature on the MC68HC711E9 ...

  • Page 17

    Technical Data — M68HC11E Family Figure 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 M68HC11E Family — Rev. 3.2 MOTOROLA Title M68HC11 E-Series Block ...

  • Page 18

    List of Figures Figure 4-13 4-14 4-15 4-16 4-17 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 7-4 7-5 7-6 7-7 Technical Data 18 Title System Configuration Options ...

  • Page 19

    Figure 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 M68HC11E Family — Rev. 3.2 MOTOROLA Title ...

  • Page 20

    List of Figures Figure 9-25 9-26 9-27 9-28 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 Simple Output Strobe Timing Diagram ...

  • Page 21

    Technical Data — M68HC11E Family Table 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 5-3 5-4 5-5 6-1 6-2 7-1 8-1 9-1 9-2 M68HC11E Family — Rev. 3.2 MOTOROLA Title Port Signal Functions . . ...

  • Page 22

    List of Tables Table 9-3 9-4 9-5 9-6 9-7 10-1 Converter Channel Assignments . . . . . . . . . . . . . . . . . . . . . . 216 10-2 A/D Converter Channel ...

  • Page 23

    Technical Data — M68HC11E Family 1.1 Contents 1.2 1.3 1.4 1.2 Introduction This document contains a detailed description of the M68HC11 E series of 8-bit microcontroller units (MCUs). These MCUs all combine the M68HC11 central processor unit (CPU) with high-performance, ...

  • Page 24

    General Description 1.3 Features Features of the E-series devices include: • • • • • • • • • • • • • • • • Technical Data 24 M68HC11 CPU Power-saving stop and wait modes Low-voltage devices available (3.0–5.5 ...

  • Page 25

    Structure See Differences among devices are noted in the table accompanying Figure M68HC11E Family — Rev. 3.2 MOTOROLA Several packaging options: – 52-pin plastic-leaded chip carrier (PLCC) – 52-pin windowed ceramic leaded chip carrier (CLCC) – 52-pin plastic ...

  • Page 26

    General Description MODA/ MODB/ LIR V XTAL EXTAL STBY OSC MODE CONTROL CLOCK LOGIC TIMER SYSTEM BUS EXPANSION ADDRESS PORT A PORT applies only to devices with EPROM/OTPROM. PPE Figure 1-1. M68HC11 E-Series Block Diagram Technical Data ...

  • Page 27

    Technical Data — M68HC11E Family 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.13.1 2.13.2 2.13.3 2.13.4 2.13.5 M68HC11E Family — Rev. 3.2 MOTOROLA Section 2. Pin Descriptions Introduction . . . . . ...

  • Page 28

    Pin Descriptions 2.2 Introduction M68HC11 E-series MCUs are available packaged in: • • • • • • Most pins on these MCUs serve two or more functions, as described in the following paragraphs. Refer to Figure assignments for the PLCC/CLCC, ...

  • Page 29

    M68HC11E Family — Rev. 3.2 MOTOROLA 1 PA0/IC3 PB7/ADDR15 5 PB6/ADDR14 6 PB5/ADDR13 7 PB4/ADDR12 8 M68HC11 E SERIES PB3/ADDR11 9 PB2/ADDR10 10 11 PB1/ADDR9 12 PB0/ADDR8 PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 ...

  • Page 30

    Pin Descriptions Technical Data 30 1 PA0/IC3 PB7/ADDR15 2 PB6/ADDR14 3 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 M68HC11 E SERIES PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PE0/AN0 10 11 PE4/AN4 12 PE1/AN1 PE5/AN5 applies only to devices ...

  • Page 31

    M68HC11E Family — Rev. 3.2 MOTOROLA MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL 8 PC0/ADDR0/DATA0 9 PC1/ADDR1/DATA1 10 PC2/ADDR2/DATA2 11 PC3/ADDR3/DATA3 12 PC4/ADDR4/DATA4 13 PC5/ADDR5/DATA5 14 PC6/ADDR6/DATA6 M68HC11 E SERIES ...

  • Page 32

    Pin Descriptions Figure 2-5. Pin Assignments for 48-Pin DIP (MC68HC811E2) 2.3 V and Power is supplied to the MCU through V supply, V power supply. Low-voltage devices in the E series operate at 3.0–5.5 volts. Very fast ...

  • Page 33

    MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. MANUAL RESET SWITCH 4.7 k OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH Figure 2-7. External Reset ...

  • Page 34

    Pin Descriptions 2.4 RESET A bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either ...

  • Page 35

    Crystal Driver and External Clock Input (XTAL and EXTAL) These two pins provide the interface for either a crystal or a CMOS- compatible clock to control the internal clock generator circuitry. The frequency applied to these pins is four ...

  • Page 36

    Pin Descriptions 2.6 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E-clock output is one fourth that of the input ...

  • Page 37

    There should be a single pullup resistor near the MCU interrupt input pin (typically 4 There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU ...

  • Page 38

    Pin Descriptions 2.10 V and These two inputs provide the reference voltages for the analog-to-digital (A/D) converter circuitry: • • For proper A/D converter operation: • • 2.11 STRA/AS The strobe A (STRA) and address strobe (AS) ...

  • Page 39

    R/W stays low during consecutive data bus write cycles, such as a double-byte store possible for data to be driven out of port C, if internal read visibility (IRV) is ...

  • Page 40

    Pin Descriptions Technical Data 40 Table 2-1. Port Signal Functions Single-Chip and Port/Bit Bootstrap Modes PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB0 PB1 PB1 PB2 PB2 PB3 PB3 PB4 PB4 PB5 PB5 PB6 PB6 PB7 PB7 PC0 ...

  • Page 41

    PA7 can function as general-purpose I timer output compare for OC1. PA7 is also the input to the pulse accumulator, even while functioning as a general-purpose I OC1 output. PA6–PA4 serve as either general-purpose outputs, timer ...

  • Page 42

    Pin Descriptions 2.13.3 Port C While in single-chip operating modes, all port C pins are general-purpose I/O pins. Port C inputs can be latched into an alternate PORTCL register by providing an input transition to the STRA signal. Port C ...

  • Page 43

    Port D Pins PD5–PD0 can be used for general-purpose I/O signals. These pins alternately serve as the serial communication interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are enabled. • • • 2.13.5 Port E Use ...

  • Page 44

    Pin Descriptions Technical Data 44 M68HC11E Family — Rev. 3.2 Pin Descriptions MOTOROLA ...

  • Page 45

    Technical Data — M68HC11E Family 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.6.5 3.3.6.6 3.3.6.7 3.3.6.8 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.7 M68HC11E Family — Rev. 3.2 MOTOROLA Section ...

  • Page 46

    Central Processor Unit (CPU) 3.2 Introduction This section presents information on M68HC11: • • • • • The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as addresses in the 64-Kbyte memory map. This is ...

  • Page 47

    A 15 3.3.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte ...

  • Page 48

    Central Processor Unit (CPU) • • 3.3.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can ...

  • Page 49

    JSR, JUMP TO SUBROUTINE MAIN PROGRAM PC $9D = JSR dd DIRECT RTN NEXT MAIN INSTR. MAIN PROGRAM PC $AD = JSR ff INDEXED, X NEXT MAIN INSTR. RTN MAIN PROGRAM PC $18 = PRE INDEXED, Y $AD = JSR ...

  • Page 50

    Central Processor Unit (CPU) When an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack, and ...

  • Page 51

    Condition Code Register (CCR) This 8-bit register contains: • • • In the M68HC11 CPU, condition codes are updated automatically by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear ...

  • Page 52

    Central Processor Unit (CPU) 3.3.6.4 Negative (N) The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be ...

  • Page 53

    XIRQ acknowledge cleared only by program instruction (TAP, where the associated bit RTI, where bit 6 of the value loaded into the CCR from the stack has been cleared). There ...

  • Page 54

    Central Processor Unit (CPU) A 4-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. ...

  • Page 55

    Direct In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00–$FF are thus accessed ...

  • Page 56

    Central Processor Unit (CPU) 3.6.6 Relative The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to ...

  • Page 57

    Table 3-2. Instruction Set (Sheet Mnemonic Operation Description ABA Add Accumulators ABX Add ( ABY Add ( ADCA (opr) Add ...

  • Page 58

    Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description BCS (rel) Branch if Carry ? Set BEQ (rel) Branch if = Zero ? BGE (rel) Branch if Zero ...

  • Page 59

    Table 3-2. Instruction Set (Sheet Mnemonic Operation Description CMPB (opr) Compare – M Memory COM (opr) Ones $FF – M Complement Memory Byte COMA Ones $FF – A Complement A COMB Ones $FF – ...

  • Page 60

    Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description INCB Increment Accumulator B INS Increment Stack Pointer INX Increment Index Register X INY Increment IY ...

  • Page 61

    Table 3-2. Instruction Set (Sheet Mnemonic Operation Description LSRB Logical Shift Right LSRD Logical Shift Right Double MUL Multiply NEG (opr) Two’s 0 – M ...

  • Page 62

    Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description RTS Return from See Figure 3–2 Subroutine SBA Subtract B from A – SBCA (opr) Subtract with A – M – C Carry ...

  • Page 63

    Table 3-2. Instruction Set (Sheet Mnemonic Operation Description TEST TEST (Only in Address Bus Counts Test Modes) TPA Transfer CC CCR Register to A TST (opr) Test for Zero or M – 0 Minus TSTA Test A ...

  • Page 64

    Central Processor Unit (CPU) Technical Data 64 Central Processor Unit (CPU) M68HC11E Family — Rev. 3.2 MOTOROLA ...

  • Page 65

    Technical Data — M68HC11E Family Section 4. Operating Modes and On-Chip Memory 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.4.2 4.4.3 4.4.3.1 4.4.3.2 4.4.3.3 4.5 4.5.1 4.5.2 4.5.3 4.6 4.6.1 4.6.1.1 4.6.1.2 4.6.1.3 4.6.1.4 4.6.1.5 4.6.1.6 4.6.2 ...

  • Page 66

    Operating Modes and On-Chip Memory 4.2 Introduction This section contains information about the operating modes and the on-chip memory for M68HC11 E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E series. Differences ...

  • Page 67

    Expanded Mode In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes: • • The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W ...

  • Page 68

    Operating Modes and On-Chip Memory 4.3.4 Bootstrap Mode When the MCU is reset in special bootstrap mode, a small on-chip read-only memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a bootloader program and a special set of interrupt ...

  • Page 69

    Refer to Figure Use of an external pullup resistor is required when using the SCI transmitter pin because port D pins are configured for wired-OR operation by the bootloader. In bootstrap mode, the ...

  • Page 70

    Operating Modes and On-Chip Memory $0000 EXT $1000 $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 4-2. Memory Map for MC68HC11E0 $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 4-3. Memory Map for MC68HC11E1 Technical Data 70 0000 ...

  • Page 71

    EXT $1000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP Figure 4-4. Memory Map for MC68HC(7)11E9 $0000 EXT $1000 EXT $9000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP * 20 Kbytes ROM/EPROM are contained in two segments of ...

  • Page 72

    Operating Modes and On-Chip Memory $0000 EXT $1000 EXT $F800 $FFFF SINGLE EXPANDED CHIP Figure 4-6. Memory Map for MC68HC811E2 Addr. Register Name Port A Data Register $1000 (PORTA) See page 134. $1001 Reserved Parallel I/O Control Register $1002 (PIOC) ...

  • Page 73

    Addr. Register Name Port C Data Register $1003 (PORTC) See page 136. Port B Data Register $1004 (PORTB) See page 136. Port C Latched Register $1005 (PORTCL) See page 137. $1006 Reserved Port C Data Direction Register $1007 (DDRC) See ...

  • Page 74

    Operating Modes and On-Chip Memory Addr. Register Name Output Compare 1 Mask $100C Register (OC1M) See page 191. Output Compare 1 Data $100D Register (OC1D) See page 192. Timer Counter Register High $100E (TCNTH) See page 193. Timer Counter Register ...

  • Page 75

    Addr. Register Name Timer Input Capture 3 Register $1015 Low (TIC3L) See page 185. Timer Output Compare 1 $1016 Register High (TOC1H) See page 188. Timer Output Compare 1 $1017 Register Low (TOC1L) See page 188. Timer Output Compare 2 ...

  • Page 76

    Operating Modes and On-Chip Memory Addr. Register Name Timer Input Capture 4/Output $101E Compare 5 Register High (TI4/O5) See page 186. Timer Input Capture 4/Output $101F Compare 5 Register Low (TI4/O5) See page 186. Timer Control Register 1 $1020 (TCTL1) ...

  • Page 77

    Addr. Register Name Pulse Accumulator Count $1027 Register (PACNT) See page 206. Serial Peripheral Control $1028 Register (SPCR) See page 173. Serial Peripheral Status $1029 Register (SPSR) See page 175. Serial Peripheral Data I/O $102A Register (SPDR) See page 176. ...

  • Page 78

    Operating Modes and On-Chip Memory Addr. Register Name Serial Communications Data $102F Register (SCDR) See page 152. Analog-to-Digital Control $1030 Status Register (ADCTL) See page 218. Analog-to-Digital Results $1031 Register 1 (ADR1) See page 220. Analog-to-Digital Results $1032 Register 2 ...

  • Page 79

    Addr. Register Name $1038 Reserved System Configuration Options $1039 Register (OPTION) See page 91. Arm/Reset COP Timer $103A Circuitry Register (COPRST) See page 111. EPROM and EEPROM $103B Programming Control Register (PPROG) See page 95. Highest Priority I Bit Interrupt ...

  • Page 80

    Operating Modes and On-Chip Memory 4.4.1 RAM and Input/Output Mapping Hardware priority is built into RAM and I/O mapping. Registers have priority over RAM and RAM has priority over ROM. When a lower priority resource is mapped at the same ...

  • Page 81

    The bootloader program is contained in the internal bootstrap ROM. This ROM, which appears as internal memory space at locations $BF00–$BFFF, is enabled only if the MCU is reset in special bootstrap mode. In expanded modes, the ROM/EPROM/OTPROM (if present) ...

  • Page 82

    Operating Modes and On-Chip Memory 4.4.2 Mode Selection The four mode variations are selected by the logic states of the MODA and MODB pins during reset. The MODA and MODB logic levels determine the logic state of SMOD and the ...

  • Page 83

    Address: Read: Write: Resets: Single chip: Expanded: Bootstrap: Test: 1. The reset values depend on the mode selected at the RESET pin rising edge. Figure 4-9. Highest Priority I-Bit Interrupt and Miscellaneous RBOOT — Read Bootstrap ROM Bit Valid only ...

  • Page 84

    Operating Modes and On-Chip Memory IRV(NE) — Internal Read Visibility (Not E) Bit IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV off. In special test mode, IRVNE is reset to ...

  • Page 85

    System Initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. Table 4-2 must be written within the first 64 cycles after reset. Table 4-2. Write Access ...

  • Page 86

    Operating Modes and On-Chip Memory 4.4.3.1 System Configuration Register The system configuration register (CONFIG) consists of an EEPROM byte and static latches that control the startup configuration of the MCU. The contents of the EEPROM byte are transferred into static ...

  • Page 87

    Address: Read: Write: Resets: Single chip: Bootstrap: Expanded: U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the ...

  • Page 88

    Operating Modes and On-Chip Memory EE[3:0] — EEPROM Mapping Bits EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to be remapped to any 4-Kbyte boundary. See NOSEC — Security Disable Bit NOSEC is invalid unless the ...

  • Page 89

    ROMON — ROM/EPROM/OTPROM Enable Bit When this bit is 0, the ROM or EPROM is disabled and that memory space becomes externally addressed. In single-chip mode, ROMON is forced enable ROM/EPROM regardless of the state of the ...

  • Page 90

    Operating Modes and On-Chip Memory REG[3:0] — 64-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. The register block, positioned at the beginning of any 4-Kbyte page ...

  • Page 91

    System Configuration Options Register The 8-bit, special-purpose system configuration options register (OPTION) sets internal system configuration options during initialization. The time protected control bits, IRQE, DLY, and CR[1:0], can be written only once after a reset and then they ...

  • Page 92

    Operating Modes and On-Chip Memory CME — Clock Monitor Enable Bit Refer to Bit 2 — Not implemented Always reads 0 CR[1:0] — COP Timer Rate Select Bits The internal E clock is divided by 2 watchdog system. These control ...

  • Page 93

    As described in the following subsections, these two methods of programming and verifying EPROM are possible: • • 4.5.1 Programming an Individual EPROM Address In this method, the MCU programs its own EPROM by controlling the PPROG register (EPROG in ...

  • Page 94

    Operating Modes and On-Chip Memory 4.5.2 Programming the EPROM with Downloaded Data When using this method, the EPROM is programmed by software while in the special test or bootstrap modes. User-developed software can be uploaded through the SCI or a ...

  • Page 95

    Address: Read: Write: Reset: 1. MC68HC711E9 only ODD — Program Odd Rows in Half of EEPROM (Test) Bit Refer to EVEN — Program Even Rows in Half of EEPROM (Test) Bit Refer to ELAT — EPROM/OTPROM Latch Control Bit When ...

  • Page 96

    Operating Modes and On-Chip Memory ERASE — Erase Mode Select Bit Refer to EELAT — EEPROM Latch Control Bit Refer to EPGM — EPROM/OTPROM/EEPROM Programming EPGM can be read any time and can be written only when ELAT = 1 ...

  • Page 97

    ELAT — EPROM/OTPROM Latch Control Bit When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when ...

  • Page 98

    Operating Modes and On-Chip Memory PGM — EPROM Programming Voltage Enable Bit PGM can be read any time and can be written only when ELAT = 1. 4.6 EEPROM Some E-series devices contain 512 bytes of on-chip EEPROM. The MC68HC811E2 ...

  • Page 99

    CSEL on-chip resistor-capacitor (RC) oscillator is used. The EEPROM programming voltage power supply voltage to the EEPROM array is not enabled until there has been a write to PPROG with EELAT set and PGM cleared. ...

  • Page 100

    Operating Modes and On-Chip Memory PTCON — Protect CONFIG Register Bit BPRT[3:0] — Block Protect Bits for EEPROM When set, these bits protect a block of EEPROM from being programmed or electronically erased. Ultraviolet light, however, can erase the entire ...

  • Page 101

    EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register (PPROG) selects and controls the EEPROM programming function. Bits in PPROG enable the programming voltage, control the latching of data to be programmed, and select the ...

  • Page 102

    Operating Modes and On-Chip Memory ERASE — Erase Mode Select Bit EELAT — EEPROM Latch Control Bit EPGM — EPROM/OTPROM/EEPROM Programming Voltage During EEPROM programming, the ROW and BYTE bits of PPROG are not used. If the frequency of the ...

  • Page 103

    EEPROM Bulk Erase This is an example of how to bulk erase the entire EEPROM. The CONFIG register is not affected in this example. 4.6.1.4 EEPROM Row Erase This example shows how to perform a fast erase of large ...

  • Page 104

    Operating Modes and On-Chip Memory 4.6.1.5 EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM. BYTEE 4.6.1.6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to ...

  • Page 105

    Resident programs, however, have unlimited access to the internal EEPROM and RAM and can read, write, or transfer ...

  • Page 106

    Operating Modes and On-Chip Memory Technical Data 106 Operating Modes and On-Chip Memory M68HC11E Family — Rev. 3.2 MOTOROLA ...

  • Page 107

    Technical Data — M68HC11E Family 5.1 Contents 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.5 5.5.1 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 M68HC11E Family — Rev. 3.2 ...

  • Page 108

    Resets and Interrupts 5.7 5.7.1 5.7.2 5.2 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current ...

  • Page 109

    Power-On Reset (POR) A positive transition on V used only for power-up conditions. POR cannot be used to detect drops in power supply voltages. A 4064 t the oscillator becomes active allows the clock generator to stabilize. If RESET ...

  • Page 110

    Resets and Interrupts 5.3.3 Computer Operating Properly (COP) Reset The MCU includes a COP system to help protect against software failures. When the COP is enabled, the software is responsible for keeping a free-running watchdog timer from timing out. When ...

  • Page 111

    Address: Read: Write: Reset: Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST) Complete this 2-step reset sequence to service the COP timer: 1. Write $55 to COPRST to arm the COP timer clearing mechanism. 2. Write $AA to COPRST to ...

  • Page 112

    Resets and Interrupts Special considerations are needed when a STOP instruction is executed and the clock monitor is enabled. Because the STOP function causes the clocks to be halted, the clock monitor function generates a reset sequence ...

  • Page 113

    CME — Clock Monitor Enable Bit This control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system clock is slow or absent. When ...

  • Page 114

    Resets and Interrupts NOCOP — COP System Disable Bit ROMON — ROM (EPROM) Enable Bit Refer to EEON — EEPROM Enable Bit Refer to 5.4 Effects of Reset When a reset condition is recognized, the internal registers and control bits ...

  • Page 115

    Central Processor Unit (CPU) After reset, the central processor unit (CPU) fetches the restart vector from the appropriate address during the first three cycles and begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after ...

  • Page 116

    Resets and Interrupts 5.4.4 Real-Time Interrupt (RTI) The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The rate control bits are cleared after reset and can be initialized by software before the real-time interrupt (RTI) system ...

  • Page 117

    Serial Peripheral Interface (SPI) The SPI system is disabled by reset. The port pins associated with this function default to being general-purpose I/O lines. 5.4.9 Analog-to-Digital (A/D) Converter The analog-to-digital (A/D) converter configuration is indeterminate after reset. The ADPU ...

  • Page 118

    Resets and Interrupts The first six interrupt sources are not maskable. The priority arrangement for these sources is: 1. POR or RESET pin 2. Clock monitor reset 3. COP watchdog reset 4. XIRQ interrupt 5. Illegal opcode interrupt 6. Software ...

  • Page 119

    I bit in the CCR any associated local bits. Interrupt vectors are not affected by priority assignment. To avoid race conditions, HPRIO can be written only while I-bit interrupts are inhibited. 5.5.1 Highest Priority Interrupt ...

  • Page 120

    Resets and Interrupts MDA — Mode Select A Bit The mode select A bit reflects the status of the MODA input pin at the rising edge of reset. Refer to On-Chip Memory IRVNE — Internal Read Visibility/Not E Bit The ...

  • Page 121

    Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) ...

  • Page 122

    Resets and Interrupts For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is cleared by the ...

  • Page 123

    Non-Maskable Interrupt Request (XIRQ) Non-maskable interrupts are useful because they can always interrupt CPU operations. The most common use for such an interrupt is for serious system problems, such as program runaway or power failure. The XIRQ input is ...

  • Page 124

    Resets and Interrupts return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. The ...

  • Page 125

    HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-5. Processing Flow Out of Reset (Sheet M68HC11E Family — Rev. 3.2 MOTOROLA EXTERNAL RESET CLOCK MONITOR ...

  • Page 126

    Resets and Interrupts STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 Figure 5-5. Processing Flow Out of Reset (Sheet Technical Data ...

  • Page 127

    BEGIN X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = 1 ? ...

  • Page 128

    Resets and Interrupts 2A Y OC2I = OC3I = OC4I = I4/O5I = TOI = PAOVI = PAII = ...

  • Page 129

    BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 5-7. Interrupt Source Resolution Within SCI 5.7 Low-Power ...

  • Page 130

    Resets and Interrupts 5.7.1 Wait Mode The WAI opcode places the MCU in wait mode, during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ, ...

  • Page 131

    Because all clocks are stopped in this mode, all internal peripheral functions also stop. The data in the internal RAM is retained as long are unchanged by stop. Therefore, when an interrupt comes to restart the system, ...

  • Page 132

    Resets and Interrupts Technical Data 132 Resets and Interrupts M68HC11E Family — Rev. 3.2 MOTOROLA ...

  • Page 133

    Technical Data — M68HC11E Family Section 6. Parallel Input/Output (I/O) Ports 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.2 Introduction All M68HC11 E-series MCUs have five input/output (I/O) ports and I/O lines, depending on ...

  • Page 134

    Parallel Input/Output (I/O) Ports Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at reset. Port pins are either driven to a specified logic level or are configured as high-impedance inputs. ...

  • Page 135

    Address: Read: Write: Reset: Figure 6-2. Pulse Accumulator Control Register (PACTL) DDRA7 — Data Direction for Port A Bit 7 Overridden if an output compare function is configured to control the PA7 pin The pulse accumulator uses port A bit ...

  • Page 136

    Parallel Input/Output (I/O) Ports 6.4 Port B In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test modes, port B pins are high-order address outputs. Address: Single-chip or bootstrap modes: Read: Write: Reset: Expanded ...

  • Page 137

    Address: Read: Write: Reset: PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into ...

  • Page 138

    Parallel Input/Output (I/O) Ports 6.6 Port D In all modes, port D bits [5:0] can be used either for general-purpose I/O or with the serial communications interface (SCI) and serial peripheral interface (SPI) subsystems. During reset, port D pins PD[5:0] ...

  • Page 139

    Port E Port E is used for general-purpose static inputs or pins that share functions with the analog-to-digital (A/D) converter system. When some port E pins are being used for general-purpose input and others are being used as A/D ...

  • Page 140

    Parallel Input/Output (I/O) Ports Full handshake modes use port C pins and the STRA and STRB lines. Input and output handshake modes are supported, and output handshake mode has a 3-stated variation. STRA is an edge-detecting input and STRB is ...

  • Page 141

    Parallel I/O Control Register The parallel handshake functions are available only in the single-chip operating mode. PIOC is a read/write register except for bit 7, which is read only. Address: Read: Write: Reset: STAF — Strobe A Interrupt Status ...

  • Page 142

    Parallel Input/Output (I/O) Ports OIN — Output or Input Handshake Select Bit HNDS must be set to 1 for this bit to have meaning. PLS — Pulsed/Interlocked Handshake Operation Bit HNDS must be set to 1 for this bit to ...

  • Page 143

    STAF Clearing HNDS OIN Sequence Read Simple PIOC with strobed STAF = 1 0 mode then read PORTCL Read Full-input PIOC with hand- STAF = 1 1 shake then read mode PORTCL Full- Read output PIOC with hand- STAF = ...

  • Page 144

    Parallel Input/Output (I/O) Ports Technical Data 144 Parallel Input/Output (I/O) Ports M68HC11E Family — Rev. 3.2 MOTOROLA ...

  • Page 145

    Technical Data — M68HC11E Family Section 7. Serial Communications Interface (SCI) 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 7.9 7.10 7.2 Introduction The serial communications interface (SCI universal asynchronous ...

  • Page 146

    Serial Communications Interface (SCI) transmitter and receiver are independent, but use the same data format and bit rate. All members of the E series contain the same SCI, with one exception. The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs ...

  • Page 147

    The block diagram, transmit serial shift register and the buffer logic at the top of the figure. TRANSMITTER BAUD RATE CLOCK 10 (11) - ...

  • Page 148

    Serial Communications Interface (SCI) 7.5 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word. This double buffered operation allows ...

  • Page 149

    RECEIVER BAUD RATE CLOCK DDD0 SEE NOTE PIN BUFFER PD0 AND CONTROL RxD SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure B-1. EVBU Schematic Diagram Figure 7-2. SCI Receiver Block Diagram M68HC11E Family — ...

  • Page 150

    Serial Communications Interface (SCI) 7.6.1 Idle-Line Wakeup To use the receiver wakeup method, establish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of receivers. This addressing scheme can take ...

  • Page 151

    SCI Error Detection Three error conditions – SCDR overrun, received bit noise, and framing – can occur during ...

  • Page 152

    Serial Communications Interface (SCI) 7.8 SCI Registers Five addressable registers are associated with the SCI: • • The SCI registers are the same for all M68HC11 E-series devices with one exception. The SCI system for MC68HC(7)11E20 contains an extra bit ...

  • Page 153

    Serial Communications Control Register 1 The SCCR1 register provides the control bits that determine word length and select the method used for the wakeup feature. Address: Read: Write: Reset: Figure 7-4. Serial Communications Control Register 1 (SCCR1) R8 — ...

  • Page 154

    Serial Communications Interface (SCI) 7.8.3 Serial Communications Control Register 2 The SCCR2 register provides the control bits that enable or disable individual SCI functions. Address: Read: Write: Reset: Figure 7-5. Serial Communications Control Register 2 (SCCR2) TIE — Transmit Interrupt ...

  • Page 155

    RWU — Receiver Wakeup Control Bit SBK — Send Break At least one character time of break is queued and sent each time SBK is written long as the SBK bit is set, break characters are queued ...

  • Page 156

    Serial Communications Interface (SCI) TC — Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC set and then writing to ...

  • Page 157

    FE — Framing Error Flag FE is set when detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR. Bit 0 — Unimplemented Always reads 0 ...

  • Page 158

    Serial Communications Interface (SCI) Prescaler Selects SCP2 SCP1 SCP0 SCR2 SCR1 SCR0 ...

  • Page 159

    RCKB — SCI Baud Rate Clock Check Bit (Test) SCR[2:0] — SCI Baud Rate Select Bits Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to The prescaler bits, SCP[2:0], determine the highest baud ...

  • Page 160

    Serial Communications Interface (SCI) 7.9 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be ...

  • Page 161

    MC68HC(7)11E20. software has noticed the status indication. The software clearing sequence for these flags is automatic. Functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. ...

  • Page 162

    Serial Communications Interface (SCI) interrupt mask for TDRE. When TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an interrupt is requested. The TC flag indicates the transmitter has completed the queue. The TCIE bit is ...

  • Page 163

    RxD remains idle. VALID SCI REQUEST M68HC11E Family — Rev. 3.2 MOTOROLA BEGIN Y FLAG RDRF = RIE = ...

  • Page 164

    Serial Communications Interface (SCI) Technical Data 164 Serial Communications Interface (SCI) M68HC11E Family — Rev. 3.2 MOTOROLA ...

  • Page 165

    Technical Data — M68HC11E Family Section 8. Serial Peripheral Interface (SPI) 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.8 8.8.1 8.8.2 8.8.3 M68HC11E Family — Rev. 3.2 MOTOROLA Introduction . . . . . . ...

  • Page 166

    Serial Peripheral Interface (SPI) 8.2 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU to communicate synchronously with peripheral devices, such as: • • • • The SPI is also capable of inter-processor communication in ...

  • Page 167

    Refer to INTERNAL MCU CLOCK DIVIDER SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST M68HC11E Family — Rev. 3.2 MOTOROLA Figure 8-1, which shows the SPI block diagram. MSB LSB 8--BIT SHIFT REGISTER READ DATA ...

  • Page 168

    Serial Peripheral Interface (SPI) 8.4 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows ...

  • Page 169

    Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects ...

  • Page 170

    Serial Peripheral Interface (SPI) 8.6.1 Master In/Slave Out MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device. The MISO line of a slave device is ...

  • Page 171

    This sets the SS pin to act as a general-purpose output rather than the dedicated input to the slave select circuit, thus inhibiting the mode fault flag. The other three lines are dedicated to the SPI whenever the ...

  • Page 172

    Serial Peripheral Interface (SPI) A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is not double buffered in the transmit direction, writes to SPDR cause data to be written directly ...

  • Page 173

    Serial Peripheral Control Register Address: Read: Write: Reset: SPIE — Serial Peripheral Interrupt Enable Bit Set the SPE bit request a hardware interrupt sequence each time the SPIF or MODF status flag is set. SPI interrupts ...

  • Page 174

    Serial Peripheral Interface (SPI) CPOL — Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value. When CPOL is set, SCK ...

  • Page 175

    Serial Peripheral Status Register Address: Read: Write: Reset: SPIF — SPI Interrupt Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a ...

  • Page 176

    Serial Peripheral Interface (SPI) 8.8.3 Serial Peripheral Data I/O Register The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs ...

  • Page 177

    Technical Data — M68HC11E Family 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 9.6 9.6.1 9.6.2 9.6.3 9.7 9.8 9.8.1 9.8.2 9.8.3 M68HC11E Family — Rev. 3.2 MOTOROLA Section ...

  • Page 178

    Timing System 9.2 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer’s programmable prescaler provides one of ...

  • Page 179

    The COP watchdog clock input (E 2 counter chain. The COP automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP is allowed to time out, a reset is generated, which ...

  • Page 180

    Timing System Control Bits PR1, PR0 1 count — overflow — 1 count — overflow — 1 count — overflow — 1 count — overflow — 9.3 Timer Structure Figure 9-2 port A pin control block includes logic for timer ...

  • Page 181

    PRESCALER DIVIDE MCU PR1 PR0 E CLK 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = ...

  • Page 182

    Timing System 9.4 Input Capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched ...

  • Page 183

    Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. 9.4.1 Timer Control Register 2 Use the control bits of this register to program input capture functions to detect a particular ...

  • Page 184

    Timing System 9.4.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and timer ...

  • Page 185

    Register name: Timer Input Capture 2 Register (High) Read: Write: Reset: Register name: Timer Input Capture 2 Register (Low) Read: Write: Reset: Register name: Timer Input Capture 3 Register (High) Read: Write: Reset: Register name: Timer Input Capture 3 Register ...

  • Page 186

    Timing System 9.4.3 Timer Input Capture 4/Output Compare 5 Register Use TI4/O5 as either an input capture register or an output compare register, depending on the function chosen for the PA3 pin. To enable input capture pin, ...

  • Page 187

    After a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match. A ...

  • Page 188

    Timing System high-order byte of an output compare register pair inhibits the output compare function for one bus cycle. This inhibition prevents inappropriate subsequent comparisons. Coherency requires a complete 16-bit read or write. However, if coherency is not needed, byte ...

  • Page 189

    Register name: Timer Output Compare 3 Register (High) Read: Write: Reset: Register name: Timer Output Compare 3 Register (Low) Read: Write: Reset: Register name: Timer Output Compare 4 Register (High) Read: Write: Reset: Register name: Timer Output Compare 4 Register ...

  • Page 190

    Timing System 9.5.2 Timer Compare Force Register The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares. These bits are set for each output compare that forced. The action taken as a result ...

  • Page 191

    Output Compare Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA[7:3]. Address: Read: Write: Reset: OC1M[7:3] — Output ...

  • Page 192

    Timing System 9.5.4 Output Compare Data Register Use this register with OC1 to specify the data that stored on the affected pin of port A after a successful OC1 compare. When a successful OC1 compare occurs, a ...

  • Page 193

    Timer Counter Register The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read addresses the most significant byte (MSB) first. A read of this address causes the least significant byte (LSB) to ...

  • Page 194

    Timing System 9.5.6 Timer Control Register 1 The bits of this register specify the action taken as a result of a successful OCx compare. Address: Read: Write: Reset: OM[2:5] — Output Mode Bits OL[2:5] — Output Level Bits These control ...

  • Page 195

    Timer Interrupt Mask 1 Register Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts. Address: Read: Write: Reset: OC1I–OC4I — Output Compare x Interrupt Enable Bits If the OCxI enable bit is ...

  • Page 196

    Timing System 9.5.8 Timer Interrupt Flag 1 Register Bits in this register indicate when timer system events have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or ...

  • Page 197

    TOI — Timer Overflow Interrupt Enable Bit RTII — Real-Time Interrupt Enable Bit Refer to PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit Refer to PAII — Pulse Accumulator Input Edge Interrupt Enable Bit Refer to Bits [3:2] — Unimplemented ...

  • Page 198

    Timing System 9.5.10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either ...

  • Page 199

    Real-Time Interrupt (RTI) The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII bit in ...

  • Page 200

    Timing System 9.6.1 Timer Interrupt Mask Register 2 This register contains the real-time interrupt enable bits. Address: Read: Write: Reset: TOI — Timer Overflow Interrupt Enable Bit RTII — Real-Time Interrupt Enable Bit PAOVI — Pulse Accumulator Overflow Interrupt Enable ...