MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 119

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.1 Highest Priority Interrupt and Miscellaneous Register
M68HC11E Family — Rev. 3.2
MOTOROLA
Reset:
Special test:
Address:
Single chip:
1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. To avoid race conditions,
HPRIO can be written only while I-bit interrupts are inhibited.
RBOOT — Read Bootstrap ROM Bit
SMOD — Special Mode Select Bit
Expanded:
Bootstrap:
RESET pin rising edge. Refer to
Has meaning only when the SMOD bit is a 1 (bootstrap mode or
special test mode). At all other times this bit is clear and cannot be
written. Refer to
for more information.
This bit reflects the inverse of the MODB input pin at the rising edge
of reset. Refer to
Memory
Read:
Write:
$103C
RBOOT
Bit 7
0
0
1
0
for more information.
Figure 5-4. Highest Priority I-Bit Interrupt
(1)
Resets and Interrupts
and Miscellaneous Register (HPRIO)
SMOD
Section 4. Operating Modes and On-Chip Memory
6
0
0
1
1
Section 4. Operating Modes and On-Chip
(1)
MDA
Table 4-1. Hardware Mode Select
5
0
1
0
1
(1)
IRVNE
4
0
0
0
1
PSEL2
3
0
0
0
0
Reset and Interrupt Priority
PSEL2
2
1
1
1
1
Resets and Interrupts
Summary.
PSEL1
Technical Data
1
1
1
1
1
PSEL0
Bit 0
119
0
0
0
0