MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 140

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Input/Output (I/O) Ports
Technical Data
140
Full handshake modes use port C pins and the STRA and STRB lines.
Input and output handshake modes are supported, and output
handshake mode has a 3-stated variation. STRA is an edge-detecting
input and STRB is a handshake output. Control and enable bits are
located in the PIOC register.
In full input handshake mode, the MCU asserts STRB to signal an
external system that it is ready to latch data. Port C logic levels are
latched into PORTCL when the STRA line is asserted by the external
system. The MCU then negates STRB. The MCU reasserts STRB after
the PORTCL register is read. In this mode, a mix of latched inputs, static
inputs, and static outputs is allowed on port C, differentiated by the data
direction bits and use of the PORTC and PORTCL registers.
In full output handshake mode, the MCU writes data to PORTCL which,
in turn, asserts the STRB output to indicate that data is ready. The
external system reads port C data and asserts the STRA input to
acknowledge that data has been received.
In the 3-state variation of output handshake mode, lines intended as
3-state handshake outputs are configured as inputs by clearing the
corresponding DDRC bits. The MCU writes data to PORTCL and asserts
STRB. The external system responds by activating the STRA input,
which forces the MCU to drive the data in PORTC out on all of the port
C lines. After the trailing edge of the active signal on STRA, the MCU
negates the STRB signal. The 3-state mode variation does not allow part
of port C to be used for static inputs while other port C pins are being
used for handshake outputs. Refer to the
Register
for further information.
Parallel Input/Output (I/O) Ports
6.9 Parallel I/O Control
M68HC11E Family — Rev. 3.2
MOTOROLA