MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 61

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
ORAA (opr)
ORAB (opr)
Mnemonic
ROR (opr)
NEG (opr)
ROL (opr)
NEGA
NEGB
RORA
RORB
LSRB
LSRD
PSHA
PSHB
PSHX
PSHY
PULA
PULB
PULX
PULY
ROLA
ROLB
NOP
MUL
RTI
Rotate Right A
Rotate Right B
Multiply 8 by 8
Right Double
Memory Byte
Rotate Left A
Rotate Left B
Complement
Complement
Complement
No operation
Accumulator
A (Inclusive)
Accumulator
Rotate Right
Logical Shift
Logical Shift
Push A onto
Push B onto
Push X onto
Push Y onto
Return from
B (Inclusive)
Pull X From
Pull A from
Pull B from
Pull Y from
Rotate Left
Operation
Stack (Lo
Stack (Lo
Stack (Hi
Stack (Hi
Interrupt
Right B
Two’s
Two’s
Two’s
Stack
Stack
Stack
Stack
First)
First)
First)
First)
OR
OR
A
B
SP = SP + 2, IX
SP = SP + 2, IY
IX
IY
SP = SP + 1, A
SP = SP + 1, B
A
B
0
0
b7
See Figure 3–2
No Operation
Description
Stk,SP = SP – 1 A
Stk,SP = SP – 1 B
C
C
C
0 – M
A + M
B + M
Stk,SP = SP – 2
Stk,SP = SP – 2
b7
b7
b7
A
b7
A
0 – A
0 – B
b0
b7
b7
b7
B
Table 3-2. Instruction Set (Sheet 5 of 7)
b7
b0
b0
b0
B
b0
D
M
A
B
A
B
C
C
C
b0
b0
b0
b0
C
Stk A
Stk B
Stk
Stk
C
B
A
B
A
A
A
A
A
B
B
B
B
B
A
B
A
B
Central Processor Unit (CPU)
Addressing
Mode
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
EXT
IND,X
IND,Y
INH
INH
INH
18
18
18
18
18
18
18
Opcode
54
04
3D
70
60
60
40
50
01
8A
9A
AA
AA
CA
DA
EA
EA
36
37
3C
3C
32
33
38
38
79
69
69
49
59
76
66
66
46
56
3B
BA
FA
Instruction
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
hh ll
ff
ff
Operand
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycles
10
12
2
3
6
6
7
2
2
2
2
3
4
4
5
2
3
4
4
5
3
3
4
5
4
4
5
6
6
6
7
2
2
6
6
7
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
Central Processor Unit (CPU)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H
Condition Codes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
—
—
—
—
—
N
0
0
Technical Data
Instruction Set
—
—
—
—
—
—
—
—
—
—
Z
—
—
—
—
—
—
—
—
—
—
V
0
0
—
—
—
—
—
—
—
—
—
—
—
C
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