EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 129

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
18 × 18 Complex Multiply
You can configure the DSP block when used in Two-Multiplier Adder
mode to implement complex multipliers using the two-multiplier adder
mode. A single half DSP block can implement one 18-bit complex
multiplier.
A complex multiplication can be written as shown in
Equation 5–4. Complex Multiplication Equation
To implement this complex multiplication within the DSP block, the real
part ((a × c) – (b × d)) is implemented using two multipliers feeding one
subtractor block while the imaginary part ((a × d) + (b × c)) is
implemented using another two multipliers feeding an adder block.
Figure 5–16
automatically assumes all inputs are using signed numbers.
(a + jb) × (c + jd) = ((a × c)) – (b × d)) + j((a × d) + (b × c))
shows an 18-bit complex multiplication. This mode
Stratix III Device Handbook, Volume 1
DSP Blocks in Stratix III Devices
Equation
5–4.
5–29