EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 362

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
11–2
Stratix III Device Handbook, Volume 1
MSEL[2..0] pins have 5-kΩ internal pull-down resistors that are always
active. During power-on reset (POR) and during reconfiguration, the
MSEL pins have to be at LVTTL V
low and logic high.
1
Notes to
(1)
(2)
(3)
(4)
Fast passive parallel (FPP)
Passive serial (PS)
Fast AS (40 MHz)
Remote system upgrade fast AS
(40 MHz)
FPP with design security feature
and/or decompression enabled
(2)
JTAG-based configuration
Table 11–1. Stratix III Configuration Schemes
Configuration Scheme
Stratix III only supports Fast AS configuration. You would need to use either
EPCS16, EPCS64, or EPCS128 devices.
These modes are only supported when using a MAX
microprocessor with flash memory for configuration. In these modes, the host
system must output a DCLK that is ×4 the data rate.
Do not leave the MSEL pins floating. Connect them to V
These pins support the non-JTAG configuration scheme used in production.
If you only use JTAG configuration, you should connect the MSEL pins to
ground.
JTAG-based configuration takes precedence over other configuration
schemes, which means MSEL pin settings are ignored.
Table
To avoid any problems with detecting an incorrect
configuration scheme, hard-wire the MSEL[] pins to V
and GND, without any pull-up or pull-down resistors. Do not
drive the MSEL[] pins by a microprocessor or another device.
(1)
11–1:
(1)
(4)
IL
MSEL2
and V
(3)
0
0
0
0
0
IH
levels to be considered a logic
MSEL1
(3)
®
0
1
1
1
0
II device or a
CCPGM
Altera Corporation
or ground.
November 2007
MSEL0
(3)
0
0
1
1
1
CCPGM