EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 225

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–1. Stratix III I/O banks
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Altera Corporation
November 2007
Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the
second output programmed as inverted.
Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT
support.
Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
Column I/O supports PCI/PCI-X with on-chip clamp diode, and row I/O supports PCI / PCI-X with external
clamp diode.
Differential clock inputs on column I/O use V
Row I/O supports the dedicated LVDS output buffer.
Column I/O banks support LVPECL standards for input clock operation.
Figure 7–1
representation only.
3.0-V PCI/PCI-X and 3.3-V LVTTL/LVCMOS are not supported in the same I/O bank.
Figure
Bank 3A
Bank 8A
is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
7–1:
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operation except LVPECL
which is supported on clk input pins only
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operation except LVPECL
which is supported on clk input pins only
Bank 3B
Bank 8B
Notes
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15 Class II,
differential HSTL-12 Class II, differential HSTL-15 Class II
(1), (2), (3), (4), (5), (6), (7), (8),
Bank 3C
Bank 8C
CCCLKIN
. All outputs use the corresponding bank V
Bank 7C
Bank 4C
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operation except LVPECL
which is supported on clk input pins only
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operation except LVPECL
which is supported on clk input pins only
Stratix III Device Handbook, Volume 1
(9)
Bank 4B
Bank 7B
Stratix III Device I/O Features
Bank 4A
Bank 7A
CCIO
.
7–7