EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 391

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Passive Serial
Configuration
Altera Corporation
November 2007
t
t
t
t
t
t
CF2ST1
DSU
DH
CH
CL
CD2UM
Table 11–8. Fast AS Timing Parameters for Stratix III Devices
Symbol
nCONFIG
Data setup time before falling edge
on
Data hold time after falling edge on
DCLK
DCLK
DCLK
CONF_DONE
DCLK
high time
low time
high to
Parameter
high to user mode
Table 11–8
You can program PS configuration of Stratix III devices using an
intelligent host, such as a MAX II device or microprocessor with flash
memory, or a download cable. In the PS scheme, an external host (a MAX
II device, embedded processor, or host PC) controls configuration.
Configuration data is clocked into the target Stratix III device via the
DATA0 pin at each rising edge of DCLK.
1
Table 11–9
scheme.
PS Configuration Using a MAX II Device as an External Host
In this configuration scheme, you can use a MAX II device as an
intelligent host that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Stratix III device. You
can store configuration data in .rbf, .hex, or .ttf format.
shows the configuration interface connections between a Stratix III device
and a MAX II device for single device configuration.
PS
Table 11–9. Stratix III MSEL Pin Settings for PS Configuration
Schemes
nSTATUS
The Stratix III decompression and design security features are
fully available when configuring your Stratix III device using PS
mode.
Configuration Scheme
shows the MSEL pin settings when using the PS configuration
shows the fast AS timing parameters for Stratix III devices.
high
Minimum
10
10
20
—
7
0
Typical
Stratix III Device Handbook, Volume 1
—
—
—
—
—
—
MSEL2 MSEL1 MSEL0
Configuring Stratix III Devices
0
Maximum
100
100
1
—
—
—
—
Figure 11–13
0
Units
ns
ns
ns
ns
μs
μs
11–31