EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 141

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Application
Examples
Altera Corporation
October 2007
FIR Example
A finite impulse response filter is a common function used in many
systems to perform spectral manipulations. The basic form is shown
in
Equation 5–5. Finite Impulse Response Flter Equation
In this equation, x(n) is the input samples to the filter, c(k) are the filter
coefficients, and y(n) are the filtered output samples. Typically, the
coefficients do not change in time in most applications such as Digital
Down Converters (DDC). FIR filters can be implemented in many forms,
the most simple being the tap-delay line approach.
Stratix III DSP block can implement various types of FIR filters very
efficiently. To form the tap-delay line, the input register stage of the DSP
block has the ability to cascade the input in a chained fashion in 18-bit
wide format. Unlike the Stratix II DSP block, which has two built-in
parallel input register scan paths, Stratix III supports only one built-in
18-bit parallel input register scan path for 288 data input.
For a pair of 18-bit input buses, the A input for the first 18-bit bus is fed
back to be registered again at the input of the second (lower) pair of
inputs. Refer to
The B input of the multiplier feeds from the general routing. You can scan
in the data in 18-bit parallel form and multiply it by the 18-bit input bus
from general routing in each cycle.
Normally in a FIR filter, the fixed data input (from general routing and
not from cascade) is the constant that needs to be multiplied by the
cascaded input. In 18-bit mode, the DSP block has enough input registers
to register the general routing signals and the cascaded signal buses
before multiplying them. This makes having eight taps for an 18-bit
cascade mode possible. Each tap can be considered a single multiplier. If
all eight multiplier inputs for the full DSP block are cascaded in a parallel
scan chain, an eight-tap FIR filter is created, as shown in
The DSP block can be concatenated to have more than eight taps by
enabling the option to output the parallel scan chain to the next (lower)
DSP block. Likewise, the output of previous (above) cascade chain is used
as an input to the current block. The first (top) multiplier in each half
block will have the option to select the 18-bit cascade chain input from the
Equation
5–5.
Figure 5–21
y(n)
for details.
=
N 1
k
∑
=
–
0
x n k
(
Stratix III Device Handbook, Volume 1
–
) c k ( )
DSP Blocks in Stratix III Devices
×
Figure
5–21.
5–41