EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 85

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 4–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
Altera Corporation
November 2007
q_a (asynch)
address_a
data_a
clk_a
wrena
rdena
Table 4–4
memory blocks in single-port mode.
Figure 4–8
single-port mode with unregistered outputs. Registering the RAM's
outputs would simply delay the q output by one clock cycle.
Port Width
Configurations
Table 4–4. Stratix III Port Width Configurations for MLABs, M9K Blocks, and
M144K Blocks (Single-Port Mode)
A
a0(old data)
shows the possible port width configurations for TriMatrix
shows timing waveforms for read and write operations in
a0
B
A
TriMatrix Embedded Memory Blocks in Stratix III Devices
C
MLABs
64×10
32×16
32×18
32×20
64×8
64×9
B
D
a1(old data)
Stratix III Device Handbook, Volume 1
M9K Blocks
512×16
512×18
256×32
256×36
a1
8K×1
4K×2
2K×4
1K×8
1K×9
E
D
F
M144K Blocks
E
16K×8
16K×9
8K×16
8K×18
4K×32
4K×36
2K×64
2K×72
4–11