EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 170

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
Figure 6–14. clkena Implementation
Notes to
(1)
(2)
6–20
Stratix III Device Handbook, Volume 1
The R1 and R2 bypass paths are not available for PLL external clock outputs.
The select line is statically controlled by a bit setting in the configuration file (.SOF or .POF).
Figure
output of clock
select mux
6–14:
clkena
Clock Enable Signals
Figure 6–14
control block is implemented in Stratix III devices.
D
In Stratix III devices, the clkena signals are supported at the clock
network level instead of at the PLL output counter level. This allows you
to gate off the clock even when a PLL is not being used. You can also use
the clkena signals to control the dedicated external clocks from the
PLLs.
enable. clkena is synchronous to the falling edge of the clock output.
Stratix III devices also have an additional metastability register that aids
in asynchronous enable/disable of the GCLK/RCLK networks. This
register can be optionally bypassed in the Quartus II software.
(1)
R1
Q
Figure 6–15
D
shows how the clock enable/disable circuit of the clock
R2
(1)
Q
shows the waveform example for a clock output
(2)
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
Altera Corporation
November 2007