EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 212

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–62
Stratix III Device Handbook, Volume 1
Table 6–22. Phase Counter Select Mapping
PHASECOUNTERSELECT[3]
0
0
0
0
0
0
0
0
1
1
1
1
Table 6–22
PHASECOUNTERSELECT setting.
The procedure to perform one dynamic phase-shift step is as follows:
1.
2.
3.
4.
5.
6.
All signals are synchronous to scanclk. They are latched on scanclk
edges and must meet t
Set phaseupdown and
Assert phasestep. Each phasestep pulse enables one phase shift.
The phasestep pulses must be at least one scanclk cycle apart.
Wait for phasedone to go low.
De-assert phasestep.
Wait for phasedone to go high.
Repeat steps 1-5 as many times as required to perform multiple
phase-shifts.
shows the PLL counter selection based on the corresponding
[2]
0
0
0
0
1
1
1
1
0
0
0
0
[1]
0
0
1
1
0
0
1
1
0
0
1
1
su
/t
h
requirements with respect to scanclk edges.
p
hasecounterselect as required.
[0]
0
1
0
1
0
1
0
1
0
1
0
1
All Output Counters
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
M
Selects
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Counter
Altera Corporation
November 2007