EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 169

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
When using the altclkctrl megafunction to implement clock source
selection (dynamic), the inputs from the clock pins feed the
inclock[0..1] ports of the multiplexer, while the PLL outputs feed
the inclock[2..3] ports. You can choose from among these inputs
using the CLKSELECT[1..0] signal.
Figure 6–13. Stratix III External PLL Output Clock Control Block
Notes to
(1)
(2)
This clock select signal can only be set through a configuration file (.SOF or .POF)
and cannot be dynamically controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_<#>_CLKOUT pin's
IOE. The PLL_<#>_CLKOUT pin is a dual-purpose pin. Therefore, this multiplexer
selects either an internal signal or the output of the clock control block.
Figure
6–13:
IOE
Internal
Logic
(2)
PLL_<#>_CLKOUT pin
7 or 10
PLL Counter
Outputs
Enable/
Disable
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
Internal
Static Clock
Select (1)
Logic
Static Clock Select
(1)
6–19