EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 334

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clocking
Figure 9–16. Bit-Order and Word Boundary for One Differential Channel
Note to
(1)
9–18
Stratix III Device Handbook, Volume 1
Operation (x8 Mode)
Operation (x4 Mode)
Operation (x8 Mode)
Transmitter Channel
Receiver Channel
Receiver Channel
These are only functional waveforms and are not intended to convey timing information.
rx_out [3..0]
rx_out [7..0]
tx_outclock
rx_outclock
rx_outclock
rx_inclock
rx_inclock
Figure
tx_out
rx_in
rx_in
9–16:
3
X
7
X X X X
2
X X X X X X X
6
X X X X X X X X
1
5
Previous Cycle
0
4
Table 9–3
differential channels. The MSB and LSB positions increase with the
number of channels used in a system.
X X X
Table 9–3. Differential Bit Naming (Part 1 of 2)
Receiver Channel
3
X X X X
Data Number
2
1
1
2
3
4
5
6
7
X X X
shows the conventions for differential bit naming for 18
0
MSB
7
X X X X
X
6
X
Current Cycle
5
X X X
X X X X X X X X
X
4 3
MSB position
X
3210
Internal 8-bit parallel data
X
2
X X X
15
23
31
39
47
55
7
X
1
LSB
X
0
X X X
X
Next Cycle
X
Note (1)
LSB position
X
X X X X 7 6 5 4
X X X X X
X
16
24
32
40
48
0
8
X
X
X
Altera Corporation
X
November 2007
X
X
X
X