EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 211

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
PHASECOUNTERSE
LECT[3:0]
PHASEUPDOWN
PHASESTEP
SCANCLK
PHASEDONE
Table 6–21. Dynamic Phase-Shifting Control Signals
Signal Name
Counter select. Four bits decoded
to select either the
counters for phase adjustment.
One address maps to select all
C
registered in the PLL on the rising
edge of
Selects dynamic phase shift
direction; 1= UP; 0= DOWN. Signal
is registered in the PLL on the rising
edge of
Logic high enables dynamic phase
shifting.
Free running clock from core used
in combination with
enable/disable dynamic phase
shifting. Shared with
dynamic reconfiguration.
When asserted it indicates to
core-logic that the phase
adjustment is complete and PLL is
ready to act on a possible second
adjustment pulse. Asserts based
on internal PLL timing. De-asserts
on rising edge of
counters. This signal is
the output clock phase-shift in real time. This adjustment is achieved by
incrementing or decrementing the VCO phase-tap selection to a given C
counter or to the M counter. The phase is shifted by 1/8 of the VCO
frequency at a time. The output clocks are active during this
phase-reconfiguration process.
Table 6–21
phase-shifting.
SCANCLK
SCANCLK
Description
SCANCLK
.
.
M
shows the control signals that are used for dynamic
PHASESTEP
or one of the
SCANCLK
.
for
to
C
Logic array or I/O pins
Logic array or I/O pin
Logic array or I/O pin
GCLK/RCLK or I/O pin
PLL reconfiguration
circuit
Clock Networks and PLLs in Stratix III Devices
Source
Stratix III Device Handbook, Volume 1
PLL reconfiguration
circuit
PLL reconfiguration
circuit
PLL reconfiguration
circuit
PLL reconfiguration
circuit
Logic array or I/O pins
Destination
6–61