EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 476

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Configuration Error Detection
Error Detection
Fundamentals
Configuration
Error Detection
User Mode Error
Detection
15–2
Stratix III Device Handbook, Volume 1
Error detection determines if the data received through a medium is
corrupted during transmission. To accomplish this, the transmitter uses a
function to calculate a checksum value for the data and appends the
checksum to the original data frame. The receiver uses the same
calculation methodology to generate a checksum for the received data
frame and compares the received checksum to the transmitted checksum.
If the two checksum values are equal, the received data frame is correct
and no data corruption occurred during transmission or storage.
The error detection CRC feature uses the same concept. When Stratix III
devices have been configured successfully and are in user mode, the error
detection CRC feature ensures the integrity of the configuration data.
1
In configuration mode, a frame-based CRC is stored within the
configuration data and contains the CRC value for each data frame.
During configuration, the Stratix III device calculates the CRC value
based on the frame of data that is received and compares it against the
frame CRC value in the data stream. Configuration continues until either
the device detects an error or configuration is complete.
In Stratix III devices, the CRC value is calculated during the configuration
stage. A parallel CRC engine generates 16 CRC check bits per frame and
then stores them into registers. The configuration random access memory
(CRAM) chain used for storing CRC check bits is 16 bits in width and its
length is equal to the frame length of the device.
Stratix III devices have built-in error detection circuitry to detect data
corruption by soft errors in the CRAM cells. This feature allows all CRAM
contents to be read and verified to match a configuration-computed CRC
value. Soft errors are changes in a CRAM’s bit state due to an ionizing
particle.
The error detection capability continuously computes the CRC of the
configured CRAM bits and compares it with the pre-calculated CRC. If
the CRCs match, there is no error in the current configuration CRAM bits.
The process of error detection continues until the device is reset (by
setting nCONFIG low).
There are two CRC error checks. One always runs during
configuration and a second optional CRC error check that runs
in the background in user mode. Both CRC error checks use the
same CRC polynomial but different error detection
implementations. For more information, refer to
Error Detection” on page 15–2
on page
15–2.
and
“User Mode Error Detection”
Altera Corporation
“Configuration
October 2007