EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 90

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Modes
4–16
Stratix III Device Handbook, Volume 1
512×16
1K×9
512×18
16K×8
8K×16
4K×32
16K×9
8K×18
4K×36
Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) (Part 2 of 2)
Table 4–8. Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode)
Read Port
Read Port
Table 4–8
in true dual-port mode.
In true dual-port mode, M9K and M144K blocks support separate
write-enable and read-enable signals. You can save power by keeping the
read-enable signal low (inactive) when not reading. Read-during-write
operations to the same address can either output new data at that location
or old data. To choose the desired behavior, set the read-during-write
behavior to either new data or old data in the RAM MegaWizard in the
Quartus II software. See
details on this behavior.
In true dual-port mode you can access any memory location at any time
from either port. When accessing the same memory location from both
ports, you must avoid possible write conflicts. A write conflict happens
when you attempt to write to the same address location from both ports
at the same time. This results in unknown data being stored to that
address location. No conflict resolution circuitry is built into the Stratix III
TriMatrix memory blocks. You must handle address conflicts external to
the RAM block.
16K
8K
v
v
v
—
—
—
v
—
—
×
×
1
8
lists the possible M144K block mixed-port width configurations
4K
8K
v
—
—
v
v
v
—
—
—
×
×
2
16
2K
“Read During Write” on page 4–21
v
—
—
4K
×
v
v
v
4
—
—
—
×
32
Write Port
Write Port
1K
v
—
—
×
16K
8
v
v
v
—
—
—
×
9
512
v
—
—
×
16
8K
v
v
v
—
—
—
×
18
Altera Corporation
1K
v
v
—
November 2007
×
9
for more
4K
512
—
—
—
v
v
v
×
v
v
—
36
×
18