EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 310

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–20. Stratix III IOE Input Registers
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
8–40
Stratix III Device Handbook, Volume 1
DQ
DQS (3)
CQn (4)
Each register block in this path can be bypassed.
There are up to three levels of resynchronization registers.
The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a
global clock line.
This input clock comes from the CQn logic block.
This resynchronization clock can come either from the PLL or from the read-leveling delay chain.
The I/O Clock Divider resides adjacent to the DQS logic block. In addition to the PLL and read levelled resync clock,
the I/O Clock Divider can also be fed by the DQS bus or CQn bus.
The half-rate data and clock signals feed into a FIFO in the FPGA core.
The dataoutbypass signal can be changed dynamically after configuration.
Figure
0
1
Double Data Rate Input Registers
8–20:
Input Reg A
Input Reg B
D
D
DFF
DFF
Q
Q
I
I
neg_reg_out
Resynchronization
Clock (5)
Input Reg C
D
DFF
Q
I
Note (1)
Synchronization
I/O Clock Divider
Registers (2)
Alignment &
(6)
Half Data Rate Registers
Half-Rate Resynchronization Clock
D
D
D
D
DFF
DFF
DFF
DFF
Q
Q
Q
Q
D
D
DFF
DFF
Q
Q
to core
to core (7)
Altera Corporation
(7)
to core (7)
November 2007
dataoutbypass (8)
0
1
0
1
to core
to core
(7)
(7)