EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 199

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
A low-bandwidth PLL can benefit a system using clock switchover.
When the clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL reacts more slowly to changes on its input clock and
takes longer to drift to a lower frequency (caused by the input stopping)
than a high-bandwidth PLL.
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL's bandwidth. Most loop filters consist of passive components such
as resistors and capacitors that take up unnecessary board space and
increase cost. With Stratix III PLLs, all the components are contained
within the device to increase performance and decrease cost.
When you specify the bandwidth setting (low, medium, or high) in the
altpll Megawizard Plug-in Manager, the Quartus II software
automatically sets the corresponding charge pump and loop filter (Icp,
R, C) values to achieve the desired bandwidth range.
Figure 6–35
using the Quartus II software. The components are the loop filter resistor,
R, the high frequency capacitor, C
I
Figure 6–35. Loop Filter Programmable Components
DN
.
PFD
shows the loop filter and the components that you can set
Clock Networks and PLLs in Stratix III Devices
H
, and the charge pump current, I
Stratix III Device Handbook, Volume 1
I
I
DN
UP
R
C
UP
C
6–49
h
or