EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 252

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

OCT Calibration
7–34
Stratix III Device Handbook, Volume 1
User Mode
During user mode, OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0]
signals are used to calibrate and serially transfer calibrated codes from
each OCT calibration block to any I/O.
controlled calibration block signal names and their descriptions.
Figure 7–18
calibration blocks are in calibration mode, and when ENAOCT is 0, all OCT
calibration blocks are in serial data transfer mode. The OCTUSRCLK clock
frequency must be 20 MHz or less.
1
OCTUSRCLK
ENAOCT
ENASER[9..0]
S2PENA_<bank#>
nCLRUSR
Table 7–8. OCT Calibration Block Ports for User Control and Description
Signal Name
You must generate all user signals on the rising edge of
OCTUSRCLK.
shows the flow of the user signal. When ENAOCT is 1, all OCT
Clock for OCT block.
Enable OCT Termination (Generated by user IP).
When
OCT serializer for the corresponding OCT
calibration block.
When
calibration for the corresponding OCT calibration
block.
Serial-to-parallel load enable per I/O bank.
Clear user.
ENAOCT
ENOCT
Table 7–8
= 0, then each signal enables the
= 1, then each signal enables OCT
Description
shows the user
Altera Corporation
November 2007