EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 846

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–334
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
Table 1–132. EP3SE110 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–133. EP3SE110 Column Pin Delay Adders for Regional Clock
Table 1–134. EP3SE110 Row Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Parameter
Strength
Current
12mA
16mA
Industrial Commercial V
Industrial Commercial V
—
—
—
—
—
—
Table 1–133
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–133
Regional Clock.
Table 1–134
Regional Clock.
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
Fast Model
Fast Model
Parameter
-0.005
1.896
1.893
0.003
1.745
1.769
and
specifies EP3SE110 Column Pin delay adders when using the
specifies EP3SE110 Row Pin delay adders when using the
t
t
t
t
CO
CO
CO
CO
Table 1–134
Industrial Commercial
CCL
CCL
2.876
2.867
0.078
0.076
2.686
2.676
—
—
—
—
-2
-2
=1.1V V
=1.1V V
Fast Model
show EP3SE110 regional clock (RCLK) adder
CCL
CCL
3.157
3.148
0.159
0.157
2.961
2.934
2.915
1.460
2.911
1.456
-3
-3
=1.1V V
=1.1V V
CCL
CCL
3.457
3.443
0.263
0.266
3.191
3.192
V
4.709 5.268 5.589 5.427 5.684
2.419 2.733 2.804 2.767 2.727
4.702 5.260 5.581 5.419 5.676
2.412 2.725 2.796 2.759 2.719
1.1V
-4
-4
CCL
=1.1V V
=1.1V V
-2
=
V
1.1V
CCL
-3
CCL
CCL
Altera Corporation
=
3.295
3.285
0.221
0.222
3.051
3.051
-4L
=1.1V V
=1.1V V
November 2007
V
1.1V
CCL
-4
-4L
=
V
1.1V
CCL
CCL
CCL
3.256
3.236
0.429
2.877
2.887
0.42
-4L
=0.9V
=0.9V
=
-4L
V
0.9V
CCL
=
Units
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns