EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 175

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
charge pump. If the charge pump receives an up signal, current is driven
into the loop filter. Conversely, if the charge pump receives a down
signal, current is drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. The loop filter also removes glitches from the
charge pump and prevents voltage over-shoot, which filters the jitter on
the VCO. The voltage from the loop filter determines how fast the VCO
operates. A divide counter (m) is inserted in the feedback loop to increase
the VCO frequency above the input reference frequency. VCO frequency
(f
reference clock (f
by the pre-scale counter (N). Therefore, the feedback clock (f
one input of the PFD is locked to the f
of the PFD.
The VCO output from Left/Right PLLs can feed seven post-scale
counters (C[0..6]), while the corresponding VCO output from
Top/Bottom PLLs can feed ten post-scale counters (C[0..9]). These
post-scale counters allow a number of harmonically related frequencies
to be produced by the PLL.
Figure 6–17
of the Stratix III PLL.
VCO
) is equal to (m) times the input reference clock (f
shows a simplified block diagram of the major components
REF
) to the PFD is equal to the input clock (f
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
REF
that is applied to the other input
REF
). The input
FB
IN
) applied to
) divided
6–25