EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 72

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Conclusion
Figure 3–10. Column I/O Block Connection to Interconnect
Conclusion
3–14
Stratix III Device Handbook, Volume 1
R4 Interconnects
Local Interconnect
Interconnects
from Logic Array
LAB Local
Control Signals
LAB
I/O Block
52 Data &
Stratix III devices consist of an array of logic blocks such as LABs,
TriMatrix memory, DSP blocks, and IOEs. These blocks communicate
with themselves and one another through the MultiTrack interconnect
structures. The Quartus II compiler automatically routes critical design
paths on faster interconnects to improve design performance and
optimize the device resources.
C4 Interconnects
C12 Interconnects
Vertical I/O Block
52
MLAB
IO_dataina[3:0]
IO_datainb[3:0]
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
Altera Corporation
October 2007
LAB