EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 253

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–18. Signals Used for User Mode Calibration
Altera Corporation
November 2007
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
OCT Calibration
Figure 7–19
OCT block[N] (where N is a calibration block number), you must assert
ENAOCT one cycle before asserting ENASER[N]. Also, nCLRUSR must be
set to low for one OCTUSRCLK cycle before ENASER[N] signal is asserted.
Assert ENASER[N] signals for 1000 OCTUSRCLK cycles to perform
OCTR
after the last ENASER is deasserted.
Serial Data Transfer
When calibration is complete, you must serially shift out the 28-bit OCT
calibration code (14-bit OCT R
calibration block to the corresponding I/O buffers. Only one OCT
calibration block can send out the codes at any given time by asserting
only one ENASER[N] signal at a time. After ENAOCT is deasserted, you
must wait at least 1 OCTUSRCLK cycle to enable any ENASER[N] signal to
begin serial transfer. In order to shift 28-bit code from OCT calibration
block[N], ENASER[N] must be asserted for exactly 28 OCTUSRCLK cycles.
Between two consecutive asserted ENASER signals there must be at least
1 OCTUSRCLK cycle gap. Refer to
S
CB1
CB0
and OCTR
CB9
CB2
S2PENA_1C
shows the user-mode signal-timing waveforms. To calibrate
OCTUSRCLK,
T
ENASER[N]
CB8
CB3
ENAOCT, nCLRUSR,
Stratix III
calibration. ENAOCT can be deasserted one clock cycle
Core
S2PENA_4C
S2PENA_6C
S
code and 14-bit OCT R
Figure 7–19
CB4
CB7
CB6
CB5
Stratix III Device Handbook, Volume 1
Bank 6A
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
Stratix III Device I/O Features
for these requirements.
T
) from each OCT
7–35