EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 277

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
Read Data
Write Data
Parity, DM, BWSn, ECC
Read Clocks/Strobes
Write Clocks
Memory Clocks
Table 8–3. Stratix III Memory Interfaces Pin Utilization
If write data is uni-directional, connect write data to a separate DQ group other than the read DQ group.
The BWSn and DM pins need to be in the write DQ group, while parity and ECC pins need to be part of the read
DQ group.
DDR2 SDRAM supports either single-ended or differential DQS signaling.
Pin Description
Table
8–3:
Table 8–3
and an external memory device.
The DQS and DQ pins use DQS phase-shift circuitry (described in the
section
compensate for PVT variations. The DQS and DQ pin locations are fixed
in the pin table. The memory interface circuitry is available in every
Stratix III I/O bank. All the memory interface pins support the I/O
standards required to support DDR3, DDR2, DDR SDRAM, QDRII+,
QDRII SRAM, and RLDRAM II devices.
DQ and DQS output signals are generated using the DDIO registers. The
clock generating the DQS signals has a 90° phase offset compared to the
clock generating the DQ signals.
DQ
DQ
DQ
Differential DQS/DQSn for DDR3/DDR2 SDRAM and RLDRAM II
Single-ended DQS for DDR2/DDR SDRAM
Complementary DQS/CQn for QDRII/+ SRAM
Any unused DQS and DQSn pin-pairs for QDRII/+ SRAM and RLDRAM II
interfaces
Any unused DQ or DQS pins with DIFFIO_RX capability for the
and
Any unused DQ or DQS pins with DIFFOUT capability for the
mem_clk[n:1]
(where n is greater than or equal to 1)
Any DIFFIO_RX pins for the
SDRAM interfaces with differential DQS signaling
Any unused DIFFOUT pins for the
in for DDR2 SDRAM interfaces with differential DQS signaling (where n is
greater than or equal to 1)
Any DIFFOUT pins for DDR2 SDRAM (with single-ended DQS signaling),
DDR SDRAM, QDRII+/QDRII SRAM, and RLDRAM II interfaces
(1)
(2)
mem_clk_n[0]
“Stratix III External Memory Interface Features” on page
summarizes the pin connections between a Stratix III device
and
in DDR3 SDRAM interfaces
mem_clk_n[n:1]
External Memory Interfaces in Stratix III Devices
Stratix III Pin Utilization
mem_clk[0]
mem_clk[n:1]
Stratix III Device Handbook, Volume 1
in DDR3 SDRAM interfaces
and
(3)
mem_clk_n[0]
and
mem_clk_n[n:1]
mem_clk[0]
(3)
in DDR2
8–21) to
8–7