EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 264

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Design Considerations
Design
Considerations
7–46
Stratix III Device Handbook, Volume 1
f
f
Altera recommends that you perform additional simulations using IBIS
models to validate that custom resistor values meet the RSDS
requirements.
For more information about the mini-LVDS I/O standard, see the
mini-LVDS Specification from the Texas Instruments web site at
www.ti.com.
While Stratix III devices feature various I/O capabilities for
high-performance and high-speed system designs, there are several other
considerations that require attention to ensure the success of those
designs.
I/O Termination
I/O termination requirements for single-ended and differential I/O
standards are discussed in this section.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not
require termination, impedance matching is necessary to reduce
reflections and improve signal integrity.
Voltage-referenced I/O standards require both an input reference
voltage, V
receiving device tracks the termination voltage of the transmitting device.
Each voltage-referenced I/O standard requires a unique termination
setup. For example, a proper resistive signal termination scheme is
critical in SSTL2 standards to produce a reliable DDR memory system
with superior noise margin.
Stratix III on-chip series and parallel termination provides the
convenience of no external components. Alternatively, you can use
external pull-up resistors to terminate the voltage-referenced I/O
standards such as SSTL and HSTL.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the signal line. Stratix III devices
provide an optional differential on-chip resistor when using LVDS.
For PCB layout guidelines, refer to
Guidelines
REF,
and
and a termination voltage, V
AN 315: Guidelines for Designing High-Speed FPGA
AN 224: High-Speed Board Layout
TT
. The reference voltage of the
Altera Corporation
November 2007
PCBs.