EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 66

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Block Interface
Memory Block
Interface
Figure 3–4. MLAB RAM Block LAB Row Interface
3–8
Stratix III Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnects
20
MLAB Local
Interconnect Region
20
TriMatrix memory consists of three types of RAM blocks: MLAB, M9K,
and M144K. This section provides a brief overview of how the different
memory blocks interface to the routing structure.
The RAM blocks in Stratix III devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The MLAB RAM
block local interconnect is driven by the R4, C4, and direct link
interconnects from adjacent LABs. The MLAB RAM blocks can
communicate with LABs on either the left or right side through these row
interconnects or with LAB columns on the left or right side with the
column interconnects. Each MLAB RAM block has up to 20 direct link
input connections from the left adjacent LAB and another 20 from the
right adjacent LAB. MLAB RAM outputs can also connect to left and right
LABs through a direct link interconnect. The MLAB RAM block has equal
opportunity for access and performance to and from LABs on either its
left or right side.
interface.
clocks
datain
Figure 3–4
LAB Row Clocks
control
signals
MLAB
address
dataout
shows the MLAB RAM block to LAB row
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnects
October 2007