EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 184

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–34
Stratix III Device Handbook, Volume 1
No-Compensation Mode
In the no-compensation mode, the PLL does not compensate for any clock
networks. This mode provides better jitter performance because the clock
feedback into the PFD passes through less circuitry. Both the PLL
internal- and external-clock outputs are phase-shifted with respect to the
PLL clock input.
clocks' phase relationship in this mode.
Figure 6–22. Phase Relationship Between PLL Clocks in No Compensation
Mode
Note to
(1)
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin.
The external clock-output pin has a phase delay relative to the clock input
pin if connected in this mode. The Quartus II software timing analyzer
reports any phase difference between the two. In normal mode, the delay
introduced by the GCLK or RCLK network is fully compensated.
Figure 6–23
relationship in this mode.
External PLL Clock Outputs (1)
The PLL clock outputs will lag the PLL input clocks depending on routine delays.
Register Clock Port (1)
Figure
PLL Clock at the
PLL Reference
shows an example waveform of the PLL clocks' phase
6–22:
Clock at the
Input Pin
Figure 6–22
Phase Aligned
shows an example waveform of the PLL
Altera Corporation
November 2007