EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 23

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Architecture
Features
Altera Corporation
November 2007
Pitch (mm)
Area (mm
Length/Width (mm/mm)
Table 1–3. FineLine BGA Package Sizes
2
Dimension
)
Table 1–3
Table 1–4
Stratix III devices are available in up to three speed grades, -2, -3, and -4,
with -2 being the fastest. Stratix III devices are offered in both commercial
and industrial temperature range ratings with leaded and lead-free
packages. Selectable Core Voltage is available in specially marked
low-voltage devices (L ordering code suffix).
The following section briefly describes the various features of the
Stratix III family of FPGAs.
Logic Array Blocks and Adaptive Logic Modules
The Logic Array Block (LAB) is composed of basic building blocks known
as Adaptive Logic Modules (ALMs) that can be configured to implement
logic, arithmetic, and register functions. Each LAB consists of ten ALMs,
carry chains, shared arithmetic chains, LAB control signals, local
interconnect, and register chain connection lines. ALMs are part of a
unique, innovative logic structure that delivers faster performance,
minimizes area, and reduces power consumption. ALMs expand the
traditional 4-input look-up table architecture to 7 inputs, increasing
performance by reducing LEs, logic levels, and associated routing. In
addition, ALMs maximize DSP performance with dedicated functionality
to efficiently implement adder trees and other complex arithmetic
Pitch (mm)
Area (mm
Length/Width (mm/mm)
Table 1–4. Hybrid FineLine BGA Package Sizes
484 Pin
23/23
1.00
529
Dimension
2
lists the Stratix III FBGA package sizes.
lists the Stratix III HBGA package sizes.
)
780 Pin
29/29
1.00
841
780 Pin
1,089
33/33
1.00
1152 Pin
1,225
35/35
1.00
Stratix III Device Handbook, Volume 1
Stratix III Device Family Overview
1152 Pin
1,600
40/40
1.00
1,517 Pin
1,600
40/40
1.00
1760 Pin
1,849
43/43
1.00
1–5