EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 453

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 13–10. IEEE Std. 1149.1 BST EXTEST Mode
Altera Corporation
November 2007
Capture Phase
In the capture phase, the
signals at the pin, OEJ and
OUTJ, are loaded into the
capture registers. The CLOCK
signals are supplied by the TAP
controller's CLOCKDR output.
Previously retained data in the
update registers drive the
PIN_OUT, INJ, and allows the
I/O pin to tri-state or drive a
signal out.
A "1" in the OEJ update
register tri-states the output
buffer.
Shift & Update Phases
In the shift phase, the
previously captured signals at
the pin, OEJ and OUTJ, are
shifted out of the boundary-scan
register via the TDO pin using
CLOCK. As data is shifted out,
the patterns for the next test
can be shifted in via the
TDI pin.
In the update phase, data is
transferred from the capture
registers to the update
registers using the UPDATE
clock. The update registers
then drive the PIN_OUT, INJ,
and allow the I/O pin to
tri-state or drive a signal out.
Figure 13–10
mode.
OUTJ
OUTJ
OEJ
OEJ
SDI
SDI
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
shows the capture, shift, and update phases of the EXTEST
0
1
0
1
0
1
0
1
0
1
0
1
SHIFT
SHIFT
CLOCK
CLOCK
Registers
D
D
D
Registers
Capture
D
D
D
Capture
Q
Q
Q
Q
Q
Q
SDO
SDO
UPDATE
UPDATE
Stratix III Device Handbook, Volume 1
Registers
D
D
D
Registers
D
D
D
Update
Update
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
0
1
0
1
0
1
MODE
MODE
PIN_IN
PIN_IN
INJ
INJ
13–15