EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 459

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1
BST for
Configured
Devices
IEEE Std. 1149.1
BST Circuitry
(Disabling)
Altera Corporation
November 2007
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When you design a board for JTAG configuration of Stratix III devices,
you need to consider the connections for the dedicated configuration
pins.
For more information on using the IEEE Std.1149.1 circuitry for device
configuration, refer to the
volume 1 of the Stratix III Device Handbook.
For a configured device, the input buffers are turned off by default for
I/O pins that are set as output only in the design file. Nevertheless,
executing the SAMPLE instruction will turn on the input buffers in the
output pins for sample operation. You can set the Quartus
always enable the input buffers on a configured device so it behaves the
same as an unconfigured device for boundary-scan testing, allowing
sample function on output pins in the design. This aspect can cause a
slight increase in standby current because the unused input buffer is
always on.
In the Quartus II software, complete the following:
1.
2.
3.
1
The IEEE Std. 1149.1 BST circuitry for Stratix III devices is enabled upon
device power-up. Because the IEEE Std. 1149.1 BST circuitry is used for
BST or in-circuit reconfiguration, you must enable the circuitry only at
specific times as mentioned in,
page
1
From the assignments menu, select Settings.
Click Assembler.
Turn on Always Enable Input Buffers.
13–20.
If you use the default setting with input disabled, you need to
convert the default BSDL file to the design-specific BSDL file
using the BSDL Customizer script. For more information
regarding BSDL file, refer to
Language (BSDL) Support” on page
If you are not using the IEEE Std. 1149.1 circuitry in Stratix III,
you should permanently disable the circuitry to ensure that you
do not inadvertently enable it when it is not required.
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
Configuring Stratix III Devices
“IEEE Std. 1149.1 BST Circuitry” on
Stratix III Device Handbook, Volume 1
“Boundary-Scan Description
13–23.
chapter in
®
II software to
13–21