EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 243
EP3SE50F780I3N
Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
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Altera Corporation
November 2007
Class II standard, you should select the 25-Ω on-chip series termination
setting (to match the 50-Ω transmission line and the near-end external
50-Ω pull-up to V
On-Chip Series Termination with Calibration
Stratix III devices support on-chip series termination with calibration in
all banks. The on-chip series termination calibration circuit compares the
total impedance of the I/O buffer to the external 25-Ω ±1% or 50-Ω ±1%
resistors connected to the R
disables the transistors until they match. The R
the intrinsic impedance of transistors. Calibration occurs at the end of
device configuration. When the calibration circuit finds the correct
impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 7–10. Stratix III On-Chip Series Termination with Calibration
Series Termination
Stratix III Driver
TT
).
V
GND
CCIO
R
R
S
S
UP
and R
Z
DN
O
Stratix III Device Handbook, Volume 1
= 50 Ω
pins, and dynamically enables or
Stratix III Device I/O Features
S
shown in
Receiving
Device
Figure 7–10
7–25
is
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