EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 900

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Glossary
1–388
Stratix III Device Handbook, Volume 2
Table 1–206. Glossary Table
Letter
G
M
O
H
K
N
F
J
L
I
f
f
f
J
JTAG Timing
Specifications
H S C L K
H S D R
H S D R D PA
Subject
—
—
—
—
—
—
—
—
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock
frequency.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(f
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(f
HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications are in the following figure:
TMS
TDO
TCK
TDI
H S D R
H S D R D PA
= 1/TUI), non-DPA.
= 1/TUI), DPA.
t
JCH
t
JPZX
t
JCP
t
JCL
t
JPCO
t
Definitions
JPSU
—
—
—
—
—
—
—
—
t
JPH
t
JPXZ
Altera Corporation
November 2007